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dec378827c
IRQ support for Broadcom's bus-axi driver bcma was merged into John Linville's wireless tree and will show up in 3.19. This patch makes use of this feature in the DTS file for the the BCM5301X SoCs. I left the PCIe controller out, because this still needs some discussion. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
146 lines
3.5 KiB
Plaintext
146 lines
3.5 KiB
Plaintext
/*
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* Broadcom BCM470X / BCM5301X ARM platform code.
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* Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
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* BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
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*
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* Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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interrupt-parent = <&gic>;
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chipcommonA {
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compatible = "simple-bus";
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ranges = <0x00000000 0x18000000 0x00001000>;
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#address-cells = <1>;
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#size-cells = <1>;
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uart0: serial@0300 {
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compatible = "ns16550";
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reg = <0x0300 0x100>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <100000000>;
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status = "disabled";
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};
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uart1: serial@0400 {
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compatible = "ns16550";
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reg = <0x0400 0x100>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <100000000>;
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status = "disabled";
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};
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};
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mpcore {
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compatible = "simple-bus";
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ranges = <0x00000000 0x19020000 0x00003000>;
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#address-cells = <1>;
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#size-cells = <1>;
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scu@0000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x0000 0x100>;
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};
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timer@0200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x0200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_periph>;
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};
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local-timer@0600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x0600 0x100>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_periph>;
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};
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gic: interrupt-controller@1000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x1000 0x1000>,
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<0x0100 0x100>;
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};
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L2: cache-controller@2000 {
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compatible = "arm,pl310-cache";
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reg = <0x2000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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/* As long as we do not have a real clock driver us this
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* fixed clock */
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clk_periph: periph {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <400000000>;
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};
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};
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axi@18000000 {
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compatible = "brcm,bus-axi";
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reg = <0x18000000 0x1000>;
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ranges = <0x00000000 0x18000000 0x00100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0x000fffff 0xffff>;
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interrupt-map =
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/* ChipCommon */
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<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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/* USB 2.0 Controller */
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<0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
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/* USB 3.0 Controller */
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<0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
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/* Ethernet Controller 0 */
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<0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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/* Ethernet Controller 1 */
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<0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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/* Ethernet Controller 2 */
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<0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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/* Ethernet Controller 3 */
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<0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
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/* NAND Controller */
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<0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
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<0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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<0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
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<0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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chipcommon: chipcommon@0 {
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reg = <0x00000000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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};
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