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e2eaa339af
Perform a mechanical translation of rd88f6281-setup.c into DT. Since the hardware differs between the A0 and A1 stepping, two dts files are used, and a .dtsi file for the common parts. The A0 part does not have a "wan" port on the switch and uses PHY address 10 to address the switch. The A1 part does have the "wan" port and uses address 0. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
26 lines
723 B
Plaintext
26 lines
723 B
Plaintext
/*
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* Marvell RD88F6181 A0 Board descrition
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*
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* Andrew Lunn <andrew@lunn.ch>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* This file contains the definitions for the board with the A0 variant of
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* the SoC. The ethernet switch does not have a "wan" port.
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*/
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/dts-v1/;
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#include "kirkwood-rd88f6281.dtsi"
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/ {
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model = "Marvell RD88f6281 Reference design, with A0 SoC";
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compatible = "marvell,rd88f6281-a0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
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dsa@0 {
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switch@0 {
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reg = <10 0>; /* MDIO address 10, switch 0 in tree */
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};
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};
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}; |