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9e0c42ea3d
- reorganize code for - add support reserve memory for mfc-v7 - consolidate exynos4 and exynos5 machine codes - add generic compatible strings for exynos4 and exynos5 - update DT with generic compatible strings - move clk related dt-binding header file in dt-bindings/clock -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJTK1NAAAoJEA0Cl+kVi2xq8ucP/0Ogcit9IddHzX5yw3wpQ6vS lX+sY15I7gGPplFPF315LFdEkv7N/QExHq5hTexLX5OHH5Teg22VvR91YgoqzhVk 0EL8uE/nKIWv/s5eipMpW9ypCE6HOHhYnjxwSEyQHjPHxgWlrO4r/1/LhlAeRL72 01uCE0sf/+HCEKujQM+i/HvGOIRV1SlNir677NppheM1PvTwlYLcc13fRaXQFblT IHEQcSkEagtau0jhO0xzN6hCZeo5IXC1DhsYFw646zWP5QnZeyeXCKL0DxzROD0f yEbhxbmWgwoJIf/5Mn4v5LhDJJ+OXswGsWgrrCbId0gd9x3UBn3Zq+fy1OXRl5cW GQG9oJXwxgU0dXMHnY0BO741zvCmoUcKfZvCEJihvYSFHJdCi0xb6GFhN/T4Jd93 hMCTH1YyjtSaVVGf5F6KnLxajm1kg8hntYF8tgheEC6oVdUB+ZNSdGO3QPl6w10j MX024K3sOlkxkjCPPz6AptU81YsgG7z8ul9jDkwDUr0Skp254uIfqDbn/+l8X0kI vN0qjtcr9hpQTuxEPNbEUXr4T9a95EiYM1lAg1QOZdN//xzgJoc7VVhyG3RML8un 2UTzy/g8V3kQ/JqfTTphMoVtodOKh60a71F0mBFl59sAbUj3tB4G1GHTfE23Tas6 theD5KDv2w4gGsE4ojWk =7IiH -----END PGP SIGNATURE----- Merge tag 'exynos-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup3 Merge "Exynos cleanup for v3.15" from Kukjin Kim: - reorganize code for - add support reserve memory for mfc-v7 - consolidate exynos4 and exynos5 machine codes - add generic compatible strings for exynos4 and exynos5 - update DT with generic compatible strings - move clk related dt-binding header file in dt-bindings/clock * tag 'exynos-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: dt-bindings: clock: Move exynos-audss-clk.h to dt-bindings/clock ARM: dts: Update Exynos DT files with generic compatible strings ARM: EXYNOS: Add generic compatible strings ARM: EXYNOS: Consolidate exynos4 and exynos5 machine files ARM: EXYNOS: Consolidate CPU init code ARM: SAMSUNG: Introduce generic Exynos4 and 5 helpers ARM: EXYNOS: Add support to reserve memory for MFC-v7 ARM: SAMSUNG: Reorganize calls to reserve memory for MFC Conflicts: arch/arm/mach-exynos/exynos.c Signed-off-by; Arnd Bergmann <arnd@arndb.de>
157 lines
3.8 KiB
Plaintext
157 lines
3.8 KiB
Plaintext
/*
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* Samsung's Exynos4210 SoC device tree source
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2010-2011 Linaro Ltd.
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* www.linaro.org
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*
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* Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
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* based board files can include this file and provide values for board specfic
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* bindings.
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*
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* Note: This file does not include device nodes for all the controllers in
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* Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
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* nodes can be added to this file.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "exynos4.dtsi"
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#include "exynos4210-pinctrl.dtsi"
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/ {
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compatible = "samsung,exynos4210", "samsung,exynos4";
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aliases {
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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};
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pd_lcd1: lcd1-power-domain@10023CA0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023CA0 0x20>;
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};
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gic: interrupt-controller@10490000 {
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cpu-offset = <0x8000>;
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};
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combiner: interrupt-controller@10440000 {
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samsung,combiner-nr = <16>;
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interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
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<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
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<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
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<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
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};
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mct@10050000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x10050000 0x800>;
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interrupt-parent = <&mct_map>;
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interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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clock-names = "fin_pll", "mct";
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mct_map: mct-map {
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = <0 &gic 0 57 0>,
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<1 &gic 0 69 0>,
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<2 &combiner 12 6>,
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<3 &combiner 12 7>,
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<4 &gic 0 42 0>,
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<5 &gic 0 48 0>;
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};
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};
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clock: clock-controller@10030000 {
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compatible = "samsung,exynos4210-clock";
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reg = <0x10030000 0x20000>;
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#clock-cells = <1>;
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupt-parent = <&combiner>;
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interrupts = <2 2>, <3 2>;
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};
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pinctrl_0: pinctrl@11400000 {
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11400000 0x1000>;
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interrupts = <0 47 0>;
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};
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pinctrl_1: pinctrl@11000000 {
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11000000 0x1000>;
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interrupts = <0 46 0>;
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wakup_eint: wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <0 32 0>;
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};
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};
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pinctrl_2: pinctrl@03860000 {
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x03860000 0x1000>;
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};
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tmu@100C0000 {
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compatible = "samsung,exynos4210-tmu";
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interrupt-parent = <&combiner>;
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reg = <0x100C0000 0x100>;
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interrupts = <2 4>;
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clocks = <&clock CLK_TMU_APBIF>;
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clock-names = "tmu_apbif";
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status = "disabled";
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};
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g2d@12800000 {
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compatible = "samsung,s5pv210-g2d";
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reg = <0x12800000 0x1000>;
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interrupts = <0 89 0>;
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clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
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clock-names = "sclk_fimg2d", "fimg2d";
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status = "disabled";
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};
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camera {
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clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
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<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
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clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
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fimc_0: fimc@11800000 {
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samsung,pix-limits = <4224 8192 1920 4224>;
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samsung,mainscaler-ext;
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samsung,cam-if;
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};
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fimc_1: fimc@11810000 {
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samsung,pix-limits = <4224 8192 1920 4224>;
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samsung,mainscaler-ext;
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samsung,cam-if;
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};
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fimc_2: fimc@11820000 {
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samsung,pix-limits = <4224 8192 1920 4224>;
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samsung,mainscaler-ext;
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samsung,lcd-wb;
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};
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fimc_3: fimc@11830000 {
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samsung,pix-limits = <1920 8192 1366 1920>;
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samsung,rotators = <0>;
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samsung,mainscaler-ext;
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samsung,lcd-wb;
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};
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};
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};
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