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06c0dd96bf
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
88 lines
3.6 KiB
Plaintext
88 lines
3.6 KiB
Plaintext
NOTES about msm drm/kms driver:
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In the current snapdragon SoC's, we have (at least) 3 different
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display controller blocks at play:
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+ MDP3 - ?? seems to be what is on geeksphone peak device
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+ MDP4 - S3 (APQ8060, touchpad), S4-pro (APQ8064, nexus4 & ifc6410)
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+ MDP5 - snapdragon 800
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(I don't have a completely clear picture on which display controller
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maps to which part #)
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Plus a handful of blocks around them for HDMI/DSI/etc output.
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And on gpu side of things:
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+ zero, one, or two 2d cores (z180)
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+ and either a2xx or a3xx 3d core.
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But, HDMI/DSI/etc blocks seem like they can be shared across multiple
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display controller blocks. And I for sure don't want to have to deal
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with N different kms devices from xf86-video-freedreno. Plus, it
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seems like we can do some clever tricks like use GPU to trigger
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pageflip after rendering completes (ie. have the kms/crtc code build
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up gpu cmdstream to update scanout and write FLUSH register after).
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So, the approach is one drm driver, with some modularity. Different
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'struct msm_kms' implementations, depending on display controller.
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And one or more 'struct msm_gpu' for the various different gpu sub-
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modules.
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(Second part is not implemented yet. So far this is just basic KMS
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driver, and not exposing any custom ioctls to userspace for now.)
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The kms module provides the plane, crtc, and encoder objects, and
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loads whatever connectors are appropriate.
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For MDP4, the mapping is:
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plane -> PIPE{RGBn,VGn} \
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crtc -> OVLP{n} + DMA{P,S,E} (??) |-> MDP "device"
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encoder -> DTV/LCDC/DSI (within MDP4) /
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connector -> HDMI/DSI/etc --> other device(s)
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Since the irq's that drm core mostly cares about are vblank/framedone,
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we'll let msm_mdp4_kms provide the irq install/uninstall/etc functions
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and treat the MDP4 block's irq as "the" irq. Even though the connectors
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may have their own irqs which they install themselves. For this reason
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the display controller is the "master" device.
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For MDP5, the mapping is:
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plane -> PIPE{RGBn,VIGn} \
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crtc -> LM (layer mixer) |-> MDP "device"
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encoder -> INTF /
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connector -> HDMI/DSI/eDP/etc --> other device(s)
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Unlike MDP4, it appears we can get by with a single encoder, rather
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than needing a different implementation for DTV, DSI, etc. (Ie. the
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register interface is same, just different bases.)
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Also unlike MDP4, with MDP5 all the IRQs for other blocks (HDMI, DSI,
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etc) are routed through MDP.
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And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
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which blocks need to be allocated to the active pipes based on fetch
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stride.
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Each connector probably ends up being a separate device, just for the
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logistics of finding/mapping io region, irq, etc. Idealy we would
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have a better way than just stashing the platform device in a global
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(ie. like DT super-node.. but I don't have any snapdragon hw yet that
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is using DT).
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Note that so far I've not been able to get any docs on the hw, and it
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seems that access to such docs would prevent me from working on the
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freedreno gallium driver. So there may be some mistakes in register
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names (I had to invent a few, since no sufficient hint was given in
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the downstream android fbdev driver), bitfield sizes, etc. My current
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state of understanding the registers is given in the envytools rnndb
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files at:
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https://github.com/freedreno/envytools/tree/master/rnndb
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(the mdp4/hdmi/dsi directories)
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These files are used both for a parser tool (in the same tree) to
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parse logged register reads/writes (both from downstream android fbdev
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driver, and this driver with register logging enabled), as well as to
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generate the register level headers.
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