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https://github.com/edk2-porting/linux-next.git
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f7be9abaa5
Move the core S3C64XX support to mach-s3c64xx as it is unlikely to be used outside of this directory. Also move the SoC header files in with it. This includes the clock, cpu, cpufreq, dma, gpiolib and pll support. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
145 lines
4.2 KiB
ArmAsm
145 lines
4.2 KiB
ArmAsm
/* linux/arch/arm/plat-s3c64xx/sleep.S
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX CPU sleep code
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/map.h>
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#undef S3C64XX_VA_GPIO
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#define S3C64XX_VA_GPIO (0x0)
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#include <mach/regs-gpio.h>
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#include <mach/gpio-bank-n.h>
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#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
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.text
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/* s3c_cpu_save
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*
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* Save enough processor state to allow the restart of the pm.c
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* code after resume.
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*
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* entry:
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* r0 = pointer to the save block
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*/
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ENTRY(s3c_cpu_save)
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stmfd sp!, { r4 - r12, lr }
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mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mrc p15, 0, r5, c3, c0, 0 @ Domain ID
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mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
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mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
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mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control
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mrc p15, 0, r9, c1, c0, 0 @ Control register
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mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
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mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls
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stmia r0, { r4 - r13 } @ Save CP registers and SP
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@@ save our state to ram
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bl s3c_pm_cb_flushcache
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@@ call final suspend code
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ldr r0, =pm_cpu_sleep
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ldr pc, [r0]
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@@ return to the caller, after the MMU is turned on.
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@@ restore the last bits of the stack and return.
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resume_with_mmu:
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ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save
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.data
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/* the next bit is code, but it requires easy access to the
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* s3c_sleep_save_phys data before the MMU is switched on, so
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* we store the code that needs this variable in the .data where
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* the value can be written to (the .text segment is RO).
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*/
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.global s3c_sleep_save_phys
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s3c_sleep_save_phys:
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.word 0
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/* Sleep magic, the word before the resume entry point so that the
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* bootloader can check for a resumeable image. */
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.word 0x2bedf00d
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/* s3c_cpu_reusme
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*
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* This is the entry point, stored by whatever method the bootloader
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* requires to get the kernel runnign again. This code expects to be
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* entered with no caches live and the MMU disabled. It will then
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* restore the MMU and other basic CP registers saved and restart
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* the kernel C code to finish the resume code.
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*/
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ENTRY(s3c_cpu_resume)
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msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
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ldr r2, =LL_UART /* for debug */
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#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
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/* Initialise the GPIO state if we are debugging via the SMDK LEDs,
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* as the uboot version supplied resets these to inputs during the
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* resume checks.
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*/
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ldr r3, =S3C64XX_PA_GPIO
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ldr r0, [ r3, #S3C64XX_GPNCON ]
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bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
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S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
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orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
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S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
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str r0, [ r3, #S3C64XX_GPNCON ]
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ldr r0, [ r3, #S3C64XX_GPNDAT ]
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bic r0, r0, #0xf << 12 @ GPN12..15
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orr r0, r0, #1 << 15 @ GPN15
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str r0, [ r3, #S3C64XX_GPNDAT ]
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#endif
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/* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches
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* are thoroughly cleaned just in case the bootloader didn't do it
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* for us. */
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mov r0, #0
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mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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@@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
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@@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches
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ldr r0, s3c_sleep_save_phys
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ldmia r0, { r4 - r13 }
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mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
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mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
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mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control
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mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
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mov r0, #0 @ restore copro access controls
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mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls
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mcr p15, 0, r0, c7, c5, 4
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ldr r2, =resume_with_mmu
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mcr p15, 0, r9, c1, c0, 0 /* turn mmu back on */
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nop
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mov pc, r2 /* jump back */
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.end
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