mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-28 15:13:55 +08:00
3162aa2f1b
Replace a BSD-style license in Code Aurora Forum authored files with an explicit GPLv2. Signed-off-by: David Brown <davidb@codeaurora.org>
278 lines
13 KiB
C
278 lines
13 KiB
C
/* Copyright (c) 2011 Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ASM_ARCH_MSM_IRQS_8960_H
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#define __ASM_ARCH_MSM_IRQS_8960_H
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/* MSM ACPU Interrupt Numbers */
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/* 0-15: STI/SGI (software triggered/generated interrupts)
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16-31: PPI (private peripheral interrupts)
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32+: SPI (shared peripheral interrupts) */
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#define GIC_PPI_START 16
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#define GIC_SPI_START 32
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#define INT_VGIC (GIC_PPI_START + 0)
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#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
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#define INT_GP_TIMER_EXP (GIC_PPI_START + 2)
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#define INT_GP_TIMER2_EXP (GIC_PPI_START + 3)
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#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 4)
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#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 5)
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#define AVS_SVICINT (GIC_PPI_START + 6)
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#define AVS_SVICINTSWDONE (GIC_PPI_START + 7)
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#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 8)
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#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 9)
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#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 10)
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#define SC_AVSCPUXDOWN (GIC_PPI_START + 11)
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#define SC_AVSCPUXUP (GIC_PPI_START + 12)
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#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 13)
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#define SC_SICCPUXEXTFAULTIRPTREQ (GIC_PPI_START + 14)
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/* PPI 15 is unused */
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#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0)
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#define SC_SICL2IRPTREQ (GIC_SPI_START + 1)
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#define SC_SICL2PERFMONIRPTREQ (GIC_SPI_START + 2)
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#define SC_SICAGCIRPTREQ (GIC_SPI_START + 3)
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#define TLMM_APCC_DIR_CONN_IRQ_0 (GIC_SPI_START + 4)
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#define TLMM_APCC_DIR_CONN_IRQ_1 (GIC_SPI_START + 5)
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#define TLMM_APCC_DIR_CONN_IRQ_2 (GIC_SPI_START + 6)
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#define TLMM_APCC_DIR_CONN_IRQ_3 (GIC_SPI_START + 7)
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#define TLMM_APCC_DIR_CONN_IRQ_4 (GIC_SPI_START + 8)
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#define TLMM_APCC_DIR_CONN_IRQ_5 (GIC_SPI_START + 9)
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#define TLMM_APCC_DIR_CONN_IRQ_6 (GIC_SPI_START + 10)
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#define TLMM_APCC_DIR_CONN_IRQ_7 (GIC_SPI_START + 11)
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#define TLMM_APCC_DIR_CONN_IRQ_8 (GIC_SPI_START + 12)
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#define TLMM_APCC_DIR_CONN_IRQ_9 (GIC_SPI_START + 13)
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#define PM8921_SEC_IRQ_103 (GIC_SPI_START + 14)
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#define PM8018_SEC_IRQ_106 (GIC_SPI_START + 15)
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#define TLMM_APCC_SUMMARY_IRQ (GIC_SPI_START + 16)
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#define SPDM_RT_1_IRQ (GIC_SPI_START + 17)
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#define SPDM_DIAG_IRQ (GIC_SPI_START + 18)
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#define RPM_APCC_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19)
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#define RPM_APCC_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20)
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#define RPM_APCC_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21)
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#define RPM_APCC_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22)
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#define RPM_APCC_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23)
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#define RPM_APCC_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24)
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#define RPM_APCC_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25)
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#define RPM_APCC_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26)
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#define SSBI2_2_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 27)
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#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 28)
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#define SSBI2_1_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 29)
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#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 30)
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#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31)
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#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32)
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#define SLIMBUS0_CORE_EE1_IRQ (GIC_SPI_START + 33)
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#define SLIMBUS0_BAM_EE1_IRQ (GIC_SPI_START + 34)
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#define Q6FW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 35)
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#define Q6SW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 36)
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#define MSS_TO_APPS_IRQ_0 (GIC_SPI_START + 37)
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#define MSS_TO_APPS_IRQ_1 (GIC_SPI_START + 38)
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#define MSS_TO_APPS_IRQ_2 (GIC_SPI_START + 39)
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#define MSS_TO_APPS_IRQ_3 (GIC_SPI_START + 40)
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#define MSS_TO_APPS_IRQ_4 (GIC_SPI_START + 41)
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#define MSS_TO_APPS_IRQ_5 (GIC_SPI_START + 42)
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#define MSS_TO_APPS_IRQ_6 (GIC_SPI_START + 43)
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#define MSS_TO_APPS_IRQ_7 (GIC_SPI_START + 44)
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#define MSS_TO_APPS_IRQ_8 (GIC_SPI_START + 45)
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#define MSS_TO_APPS_IRQ_9 (GIC_SPI_START + 46)
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#define VPE_IRQ (GIC_SPI_START + 47)
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#define VFE_IRQ (GIC_SPI_START + 48)
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#define VCODEC_IRQ (GIC_SPI_START + 49)
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#define TV_ENC_IRQ (GIC_SPI_START + 50)
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#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51)
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#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52)
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#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53)
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#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54)
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#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55)
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#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56)
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#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57)
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#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58)
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#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59)
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#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60)
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#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61)
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#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62)
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#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63)
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#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64)
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#define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65)
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#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66)
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#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67)
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#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68)
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#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69)
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#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70)
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#define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71)
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#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72)
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#define ROT_IRQ (GIC_SPI_START + 73)
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#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74)
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#define MDP_IRQ (GIC_SPI_START + 75)
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#define JPEGD_IRQ (GIC_SPI_START + 76)
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#define JPEG_IRQ (GIC_SPI_START + 77)
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#define MMSS_IMEM_IRQ (GIC_SPI_START + 78)
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#define HDMI_IRQ (GIC_SPI_START + 79)
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#define GFX3D_IRQ (GIC_SPI_START + 80)
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#define GFX2D0_IRQ (GIC_SPI_START + 81)
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#define DSI1_IRQ (GIC_SPI_START + 82)
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#define CSI_1_IRQ (GIC_SPI_START + 83)
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#define CSI_0_IRQ (GIC_SPI_START + 84)
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#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85)
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#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86)
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#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87)
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#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88)
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#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89)
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#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90)
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#define TOP_IMEM_IRQ (GIC_SPI_START + 91)
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#define FABRIC_SYS_IRQ (GIC_SPI_START + 92)
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#define FABRIC_APPS_IRQ (GIC_SPI_START + 93)
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#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
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#define SDC4_BAM_IRQ (GIC_SPI_START + 95)
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#define SDC3_BAM_IRQ (GIC_SPI_START + 96)
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#define SDC2_BAM_IRQ (GIC_SPI_START + 97)
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#define SDC1_BAM_IRQ (GIC_SPI_START + 98)
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#define FABRIC_SPS_IRQ (GIC_SPI_START + 99)
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#define USB1_HS_IRQ (GIC_SPI_START + 100)
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#define SDC4_IRQ_0 (GIC_SPI_START + 101)
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#define SDC3_IRQ_0 (GIC_SPI_START + 102)
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#define SDC2_IRQ_0 (GIC_SPI_START + 103)
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#define SDC1_IRQ_0 (GIC_SPI_START + 104)
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#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
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#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106)
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#define SPS_MTI_0 (GIC_SPI_START + 107)
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#define SPS_MTI_1 (GIC_SPI_START + 108)
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#define SPS_MTI_2 (GIC_SPI_START + 109)
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#define SPS_MTI_3 (GIC_SPI_START + 110)
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#define SPS_MTI_4 (GIC_SPI_START + 111)
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#define SPS_MTI_5 (GIC_SPI_START + 112)
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#define SPS_MTI_6 (GIC_SPI_START + 113)
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#define SPS_MTI_7 (GIC_SPI_START + 114)
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#define SPS_MTI_8 (GIC_SPI_START + 115)
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#define SPS_MTI_9 (GIC_SPI_START + 116)
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#define SPS_MTI_10 (GIC_SPI_START + 117)
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#define SPS_MTI_11 (GIC_SPI_START + 118)
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#define SPS_MTI_12 (GIC_SPI_START + 119)
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#define SPS_MTI_13 (GIC_SPI_START + 120)
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#define SPS_MTI_14 (GIC_SPI_START + 121)
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#define SPS_MTI_15 (GIC_SPI_START + 122)
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#define SPS_MTI_16 (GIC_SPI_START + 123)
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#define SPS_MTI_17 (GIC_SPI_START + 124)
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#define SPS_MTI_18 (GIC_SPI_START + 125)
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#define SPS_MTI_19 (GIC_SPI_START + 126)
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#define SPS_MTI_20 (GIC_SPI_START + 127)
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#define SPS_MTI_21 (GIC_SPI_START + 128)
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#define SPS_MTI_22 (GIC_SPI_START + 129)
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#define SPS_MTI_23 (GIC_SPI_START + 130)
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#define SPS_MTI_24 (GIC_SPI_START + 131)
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#define SPS_MTI_25 (GIC_SPI_START + 132)
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#define SPS_MTI_26 (GIC_SPI_START + 133)
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#define SPS_MTI_27 (GIC_SPI_START + 134)
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#define SPS_MTI_28 (GIC_SPI_START + 135)
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#define SPS_MTI_29 (GIC_SPI_START + 136)
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#define SPS_MTI_30 (GIC_SPI_START + 137)
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#define SPS_MTI_31 (GIC_SPI_START + 138)
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#define CSIPHY_4LN_IRQ (GIC_SPI_START + 139)
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#define CSIPHY_2LN_IRQ (GIC_SPI_START + 140)
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#define USB2_IRQ (GIC_SPI_START + 141)
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#define USB1_IRQ (GIC_SPI_START + 142)
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#define TSSC_SSBI_IRQ (GIC_SPI_START + 143)
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#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144)
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#define TSSC_PENUP_IRQ (GIC_SPI_START + 145)
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#define GSBI1_UARTDM_IRQ (GIC_SPI_START + 146)
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#define GSBI1_QUP_IRQ (GIC_SPI_START + 147)
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#define GSBI2_UARTDM_IRQ (GIC_SPI_START + 148)
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#define GSBI2_QUP_IRQ (GIC_SPI_START + 149)
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#define GSBI3_UARTDM_IRQ (GIC_SPI_START + 150)
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#define GSBI3_QUP_IRQ (GIC_SPI_START + 151)
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#define GSBI4_UARTDM_IRQ (GIC_SPI_START + 152)
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#define GSBI4_QUP_IRQ (GIC_SPI_START + 153)
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#define GSBI5_UARTDM_IRQ (GIC_SPI_START + 154)
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#define GSBI5_QUP_IRQ (GIC_SPI_START + 155)
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#define GSBI6_UARTDM_IRQ (GIC_SPI_START + 156)
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#define GSBI6_QUP_IRQ (GIC_SPI_START + 157)
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#define GSBI7_UARTDM_IRQ (GIC_SPI_START + 158)
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#define GSBI7_QUP_IRQ (GIC_SPI_START + 159)
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#define GSBI8_UARTDM_IRQ (GIC_SPI_START + 160)
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#define GSBI8_QUP_IRQ (GIC_SPI_START + 161)
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#define TSIF_TSPP_IRQ (GIC_SPI_START + 162)
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#define TSIF_BAM_IRQ (GIC_SPI_START + 163)
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#define TSIF2_IRQ (GIC_SPI_START + 164)
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#define TSIF1_IRQ (GIC_SPI_START + 165)
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#define DSI2_IRQ (GIC_SPI_START + 166)
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#define ISPIF_IRQ (GIC_SPI_START + 167)
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#define MSMC_SC_SEC_TMR_IRQ (GIC_SPI_START + 168)
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#define MSMC_SC_SEC_WDOG_BARK_IRQ (GIC_SPI_START + 169)
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#define INT_ADM0_SCSS_0_IRQ (GIC_SPI_START + 170)
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#define INT_ADM0_SCSS_1_IRQ (GIC_SPI_START + 171)
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#define INT_ADM0_SCSS_2_IRQ (GIC_SPI_START + 172)
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#define INT_ADM0_SCSS_3_IRQ (GIC_SPI_START + 173)
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#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174)
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#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175)
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#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176)
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#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177)
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#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178)
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#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179)
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#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180)
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#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181)
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#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182)
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#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183)
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#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184)
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#define HSDDRX_EBI1CH0_IRQ (GIC_SPI_START + 185)
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#define HSDDRX_EBI1CH1_IRQ (GIC_SPI_START + 186)
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#define SDC5_BAM_IRQ (GIC_SPI_START + 187)
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#define SDC5_IRQ_0 (GIC_SPI_START + 188)
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#define GSBI9_UARTDM_IRQ (GIC_SPI_START + 189)
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#define GSBI9_QUP_IRQ (GIC_SPI_START + 190)
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#define GSBI10_UARTDM_IRQ (GIC_SPI_START + 191)
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#define GSBI10_QUP_IRQ (GIC_SPI_START + 192)
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#define GSBI11_UARTDM_IRQ (GIC_SPI_START + 193)
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#define GSBI11_QUP_IRQ (GIC_SPI_START + 194)
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#define GSBI12_UARTDM_IRQ (GIC_SPI_START + 195)
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#define GSBI12_QUP_IRQ (GIC_SPI_START + 196)
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#define RIVA_APSS_LTECOEX_IRQ (GIC_SPI_START + 197)
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#define RIVA_APSS_SPARE_IRQ (GIC_SPI_START + 198)
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#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ (GIC_SPI_START + 199)
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#define RIVA_ASS_RESET_DONE_IRQ (GIC_SPI_START + 200)
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#define RIVA_APSS_ASIC_IRQ (GIC_SPI_START + 201)
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#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ (GIC_SPI_START + 202)
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#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ (GIC_SPI_START + 203)
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#define RIVA_APPS_WLAM_SMSM_IRQ (GIC_SPI_START + 204)
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#define RIVA_APPS_LOG_CTRL_IRQ (GIC_SPI_START + 205)
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#define RIVA_APPS_FM_CTRL_IRQ (GIC_SPI_START + 206)
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#define RIVA_APPS_HCI_IRQ (GIC_SPI_START + 207)
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#define RIVA_APPS_WLAN_CTRL_IRQ (GIC_SPI_START + 208)
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#define A2_BAM_IRQ (GIC_SPI_START + 209)
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#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210)
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#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211)
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#define GFX2D1_IRQ (GIC_SPI_START + 212)
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#define PPSS_WDOG_TIMER_IRQ (GIC_SPI_START + 213)
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#define SPS_SLIMBUS_CORE_EE0_IRQ (GIC_SPI_START + 214)
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#define SPS_SLIMBUS_BAM_EE0_IRQ (GIC_SPI_START + 215)
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#define QDSS_ETB_IRQ (GIC_SPI_START + 216)
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#define QDSS_CTI2KPSS_CPU1_IRQ (GIC_SPI_START + 217)
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#define QDSS_CTI2KPSS_CPU0_IRQ (GIC_SPI_START + 218)
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#define TLMM_APCC_DIR_CONN_IRQ_16 (GIC_SPI_START + 219)
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#define TLMM_APCC_DIR_CONN_IRQ_17 (GIC_SPI_START + 220)
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#define TLMM_APCC_DIR_CONN_IRQ_18 (GIC_SPI_START + 221)
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#define TLMM_APCC_DIR_CONN_IRQ_19 (GIC_SPI_START + 222)
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#define TLMM_APCC_DIR_CONN_IRQ_20 (GIC_SPI_START + 223)
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#define TLMM_APCC_DIR_CONN_IRQ_21 (GIC_SPI_START + 224)
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#define PM8921_SEC_IRQ_104 (GIC_SPI_START + 225)
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#define PM8018_SEC_IRQ_107 (GIC_SPI_START + 226)
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/* For now, use the maximum number of interrupts until a pending GIC issue
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* is sorted out */
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#define NR_MSM_IRQS 1020
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#define NR_BOARD_IRQS 0
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#define NR_GPIO_IRQS 0
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#endif
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