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ac3167257b
At over 4000 #includes, <linux/platform_device.h> is the 9th most #included header file in the Linux kernel. It does not need <linux/mod_devicetable.h>, so drop that header and explicitly add <linux/mod_devicetable.h> to source files that need it. 4146 #include <linux/platform_device.h> After this patch, there are 225 files that use <linux/mod_devicetable.h>, for a reduction of around 3900 times that <linux/mod_devicetable.h> does not have to be read & parsed. 225 #include <linux/mod_devicetable.h> This patch was build-tested on 20 different arch-es. It also makes these drivers SubmitChecklist#1 compliant. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kbuild test robot <lkp@intel.com> # drivers/media/platform/vimc/ Reported-by: kbuild test robot <lkp@intel.com> # drivers/pinctrl/pinctrl-u300.c Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
600 lines
17 KiB
C
600 lines
17 KiB
C
/*
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* Driver for EIP97 cryptographic accelerator.
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*
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* Copyright (c) 2016 Ryder Lee <ryder.lee@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/clk.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include "mtk-platform.h"
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#define MTK_BURST_SIZE_MSK GENMASK(7, 4)
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#define MTK_BURST_SIZE(x) ((x) << 4)
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#define MTK_DESC_SIZE(x) ((x) << 0)
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#define MTK_DESC_OFFSET(x) ((x) << 16)
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#define MTK_DESC_FETCH_SIZE(x) ((x) << 0)
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#define MTK_DESC_FETCH_THRESH(x) ((x) << 16)
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#define MTK_DESC_OVL_IRQ_EN BIT(25)
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#define MTK_DESC_ATP_PRESENT BIT(30)
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#define MTK_DFSE_IDLE GENMASK(3, 0)
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#define MTK_DFSE_THR_CTRL_EN BIT(30)
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#define MTK_DFSE_THR_CTRL_RESET BIT(31)
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#define MTK_DFSE_RING_ID(x) (((x) >> 12) & GENMASK(3, 0))
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#define MTK_DFSE_MIN_DATA(x) ((x) << 0)
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#define MTK_DFSE_MAX_DATA(x) ((x) << 8)
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#define MTK_DFE_MIN_CTRL(x) ((x) << 16)
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#define MTK_DFE_MAX_CTRL(x) ((x) << 24)
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#define MTK_IN_BUF_MIN_THRESH(x) ((x) << 8)
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#define MTK_IN_BUF_MAX_THRESH(x) ((x) << 12)
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#define MTK_OUT_BUF_MIN_THRESH(x) ((x) << 0)
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#define MTK_OUT_BUF_MAX_THRESH(x) ((x) << 4)
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#define MTK_IN_TBUF_SIZE(x) (((x) >> 4) & GENMASK(3, 0))
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#define MTK_IN_DBUF_SIZE(x) (((x) >> 8) & GENMASK(3, 0))
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#define MTK_OUT_DBUF_SIZE(x) (((x) >> 16) & GENMASK(3, 0))
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#define MTK_CMD_FIFO_SIZE(x) (((x) >> 8) & GENMASK(3, 0))
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#define MTK_RES_FIFO_SIZE(x) (((x) >> 12) & GENMASK(3, 0))
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#define MTK_PE_TK_LOC_AVL BIT(2)
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#define MTK_PE_PROC_HELD BIT(14)
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#define MTK_PE_TK_TIMEOUT_EN BIT(22)
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#define MTK_PE_INPUT_DMA_ERR BIT(0)
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#define MTK_PE_OUTPUT_DMA_ERR BIT(1)
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#define MTK_PE_PKT_PORC_ERR BIT(2)
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#define MTK_PE_PKT_TIMEOUT BIT(3)
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#define MTK_PE_FATAL_ERR BIT(14)
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#define MTK_PE_INPUT_DMA_ERR_EN BIT(16)
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#define MTK_PE_OUTPUT_DMA_ERR_EN BIT(17)
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#define MTK_PE_PKT_PORC_ERR_EN BIT(18)
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#define MTK_PE_PKT_TIMEOUT_EN BIT(19)
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#define MTK_PE_FATAL_ERR_EN BIT(30)
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#define MTK_PE_INT_OUT_EN BIT(31)
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#define MTK_HIA_SIGNATURE ((u16)0x35ca)
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#define MTK_HIA_DATA_WIDTH(x) (((x) >> 25) & GENMASK(1, 0))
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#define MTK_HIA_DMA_LENGTH(x) (((x) >> 20) & GENMASK(4, 0))
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#define MTK_CDR_STAT_CLR GENMASK(4, 0)
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#define MTK_RDR_STAT_CLR GENMASK(7, 0)
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#define MTK_AIC_INT_MSK GENMASK(5, 0)
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#define MTK_AIC_VER_MSK (GENMASK(15, 0) | GENMASK(27, 20))
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#define MTK_AIC_VER11 0x011036c9
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#define MTK_AIC_VER12 0x012036c9
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#define MTK_AIC_G_CLR GENMASK(30, 20)
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/**
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* EIP97 is an integrated security subsystem to accelerate cryptographic
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* functions and protocols to offload the host processor.
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* Some important hardware modules are briefly introduced below:
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*
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* Host Interface Adapter(HIA) - the main interface between the host
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* system and the hardware subsystem. It is responsible for attaching
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* processing engine to the specific host bus interface and provides a
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* standardized software view for off loading tasks to the engine.
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*
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* Command Descriptor Ring Manager(CDR Manager) - keeps track of how many
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* CD the host has prepared in the CDR. It monitors the fill level of its
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* CD-FIFO and if there's sufficient space for the next block of descriptors,
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* then it fires off a DMA request to fetch a block of CDs.
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*
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* Data fetch engine(DFE) - It is responsible for parsing the CD and
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* setting up the required control and packet data DMA transfers from
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* system memory to the processing engine.
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*
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* Result Descriptor Ring Manager(RDR Manager) - same as CDR Manager,
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* but target is result descriptors, Moreover, it also handles the RD
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* updates under control of the DSE. For each packet data segment
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* processed, the DSE triggers the RDR Manager to write the updated RD.
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* If triggered to update, the RDR Manager sets up a DMA operation to
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* copy the RD from the DSE to the correct location in the RDR.
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*
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* Data Store Engine(DSE) - It is responsible for parsing the prepared RD
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* and setting up the required control and packet data DMA transfers from
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* the processing engine to system memory.
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*
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* Advanced Interrupt Controllers(AICs) - receive interrupt request signals
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* from various sources and combine them into one interrupt output.
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* The AICs are used by:
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* - One for the HIA global and processing engine interrupts.
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* - The others for the descriptor ring interrupts.
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*/
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/* Cryptographic engine capabilities */
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struct mtk_sys_cap {
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/* host interface adapter */
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u32 hia_ver;
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u32 hia_opt;
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/* packet engine */
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u32 pkt_eng_opt;
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/* global hardware */
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u32 hw_opt;
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};
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static void mtk_desc_ring_link(struct mtk_cryp *cryp, u32 mask)
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{
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/* Assign rings to DFE/DSE thread and enable it */
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writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DFE_THR_CTRL);
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writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DSE_THR_CTRL);
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}
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static void mtk_dfe_dse_buf_setup(struct mtk_cryp *cryp,
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struct mtk_sys_cap *cap)
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{
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u32 width = MTK_HIA_DATA_WIDTH(cap->hia_opt) + 2;
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u32 len = MTK_HIA_DMA_LENGTH(cap->hia_opt) - 1;
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u32 ipbuf = min((u32)MTK_IN_DBUF_SIZE(cap->hw_opt) + width, len);
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u32 opbuf = min((u32)MTK_OUT_DBUF_SIZE(cap->hw_opt) + width, len);
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u32 itbuf = min((u32)MTK_IN_TBUF_SIZE(cap->hw_opt) + width, len);
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writel(MTK_DFSE_MIN_DATA(ipbuf - 1) |
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MTK_DFSE_MAX_DATA(ipbuf) |
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MTK_DFE_MIN_CTRL(itbuf - 1) |
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MTK_DFE_MAX_CTRL(itbuf),
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cryp->base + DFE_CFG);
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writel(MTK_DFSE_MIN_DATA(opbuf - 1) |
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MTK_DFSE_MAX_DATA(opbuf),
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cryp->base + DSE_CFG);
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writel(MTK_IN_BUF_MIN_THRESH(ipbuf - 1) |
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MTK_IN_BUF_MAX_THRESH(ipbuf),
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cryp->base + PE_IN_DBUF_THRESH);
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writel(MTK_IN_BUF_MIN_THRESH(itbuf - 1) |
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MTK_IN_BUF_MAX_THRESH(itbuf),
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cryp->base + PE_IN_TBUF_THRESH);
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writel(MTK_OUT_BUF_MIN_THRESH(opbuf - 1) |
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MTK_OUT_BUF_MAX_THRESH(opbuf),
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cryp->base + PE_OUT_DBUF_THRESH);
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writel(0, cryp->base + PE_OUT_TBUF_THRESH);
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writel(0, cryp->base + PE_OUT_BUF_CTRL);
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}
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static int mtk_dfe_dse_state_check(struct mtk_cryp *cryp)
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{
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int ret = -EINVAL;
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u32 val;
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/* Check for completion of all DMA transfers */
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val = readl(cryp->base + DFE_THR_STAT);
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if (MTK_DFSE_RING_ID(val) == MTK_DFSE_IDLE) {
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val = readl(cryp->base + DSE_THR_STAT);
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if (MTK_DFSE_RING_ID(val) == MTK_DFSE_IDLE)
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ret = 0;
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}
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if (!ret) {
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/* Take DFE/DSE thread out of reset */
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writel(0, cryp->base + DFE_THR_CTRL);
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writel(0, cryp->base + DSE_THR_CTRL);
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} else {
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return -EBUSY;
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}
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return 0;
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}
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static int mtk_dfe_dse_reset(struct mtk_cryp *cryp)
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{
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int err;
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/* Reset DSE/DFE and correct system priorities for all rings. */
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writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DFE_THR_CTRL);
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writel(0, cryp->base + DFE_PRIO_0);
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writel(0, cryp->base + DFE_PRIO_1);
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writel(0, cryp->base + DFE_PRIO_2);
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writel(0, cryp->base + DFE_PRIO_3);
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writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DSE_THR_CTRL);
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writel(0, cryp->base + DSE_PRIO_0);
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writel(0, cryp->base + DSE_PRIO_1);
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writel(0, cryp->base + DSE_PRIO_2);
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writel(0, cryp->base + DSE_PRIO_3);
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err = mtk_dfe_dse_state_check(cryp);
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if (err)
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return err;
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return 0;
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}
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static void mtk_cmd_desc_ring_setup(struct mtk_cryp *cryp,
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int i, struct mtk_sys_cap *cap)
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{
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/* Full descriptor that fits FIFO minus one */
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u32 count =
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((1 << MTK_CMD_FIFO_SIZE(cap->hia_opt)) / MTK_DESC_SZ) - 1;
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/* Temporarily disable external triggering */
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writel(0, cryp->base + CDR_CFG(i));
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/* Clear CDR count */
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writel(MTK_CNT_RST, cryp->base + CDR_PREP_COUNT(i));
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writel(MTK_CNT_RST, cryp->base + CDR_PROC_COUNT(i));
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writel(0, cryp->base + CDR_PREP_PNTR(i));
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writel(0, cryp->base + CDR_PROC_PNTR(i));
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writel(0, cryp->base + CDR_DMA_CFG(i));
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/* Configure CDR host address space */
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writel(0, cryp->base + CDR_BASE_ADDR_HI(i));
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writel(cryp->ring[i]->cmd_dma, cryp->base + CDR_BASE_ADDR_LO(i));
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writel(MTK_DESC_RING_SZ, cryp->base + CDR_RING_SIZE(i));
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/* Clear and disable all CDR interrupts */
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writel(MTK_CDR_STAT_CLR, cryp->base + CDR_STAT(i));
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/*
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* Set command descriptor offset and enable additional
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* token present in descriptor.
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*/
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writel(MTK_DESC_SIZE(MTK_DESC_SZ) |
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MTK_DESC_OFFSET(MTK_DESC_OFF) |
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MTK_DESC_ATP_PRESENT,
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cryp->base + CDR_DESC_SIZE(i));
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writel(MTK_DESC_FETCH_SIZE(count * MTK_DESC_OFF) |
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MTK_DESC_FETCH_THRESH(count * MTK_DESC_SZ),
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cryp->base + CDR_CFG(i));
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}
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static void mtk_res_desc_ring_setup(struct mtk_cryp *cryp,
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int i, struct mtk_sys_cap *cap)
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{
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u32 rndup = 2;
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u32 count = ((1 << MTK_RES_FIFO_SIZE(cap->hia_opt)) / rndup) - 1;
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/* Temporarily disable external triggering */
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writel(0, cryp->base + RDR_CFG(i));
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/* Clear RDR count */
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writel(MTK_CNT_RST, cryp->base + RDR_PREP_COUNT(i));
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writel(MTK_CNT_RST, cryp->base + RDR_PROC_COUNT(i));
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writel(0, cryp->base + RDR_PREP_PNTR(i));
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writel(0, cryp->base + RDR_PROC_PNTR(i));
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writel(0, cryp->base + RDR_DMA_CFG(i));
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/* Configure RDR host address space */
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writel(0, cryp->base + RDR_BASE_ADDR_HI(i));
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writel(cryp->ring[i]->res_dma, cryp->base + RDR_BASE_ADDR_LO(i));
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writel(MTK_DESC_RING_SZ, cryp->base + RDR_RING_SIZE(i));
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writel(MTK_RDR_STAT_CLR, cryp->base + RDR_STAT(i));
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/*
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* RDR manager generates update interrupts on a per-completed-packet,
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* and the rd_proc_thresh_irq interrupt is fired when proc_pkt_count
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* for the RDR exceeds the number of packets.
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*/
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writel(MTK_RDR_PROC_THRESH | MTK_RDR_PROC_MODE,
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cryp->base + RDR_THRESH(i));
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/*
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* Configure a threshold and time-out value for the processed
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* result descriptors (or complete packets) that are written to
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* the RDR.
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*/
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writel(MTK_DESC_SIZE(MTK_DESC_SZ) | MTK_DESC_OFFSET(MTK_DESC_OFF),
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cryp->base + RDR_DESC_SIZE(i));
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/*
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* Configure HIA fetch size and fetch threshold that are used to
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* fetch blocks of multiple descriptors.
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*/
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writel(MTK_DESC_FETCH_SIZE(count * MTK_DESC_OFF) |
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MTK_DESC_FETCH_THRESH(count * rndup) |
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MTK_DESC_OVL_IRQ_EN,
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cryp->base + RDR_CFG(i));
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}
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static int mtk_packet_engine_setup(struct mtk_cryp *cryp)
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{
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struct mtk_sys_cap cap;
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int i, err;
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u32 val;
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cap.hia_ver = readl(cryp->base + HIA_VERSION);
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cap.hia_opt = readl(cryp->base + HIA_OPTIONS);
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cap.hw_opt = readl(cryp->base + EIP97_OPTIONS);
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if (!(((u16)cap.hia_ver) == MTK_HIA_SIGNATURE))
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return -EINVAL;
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/* Configure endianness conversion method for master (DMA) interface */
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writel(0, cryp->base + EIP97_MST_CTRL);
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/* Set HIA burst size */
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val = readl(cryp->base + HIA_MST_CTRL);
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val &= ~MTK_BURST_SIZE_MSK;
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val |= MTK_BURST_SIZE(5);
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writel(val, cryp->base + HIA_MST_CTRL);
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err = mtk_dfe_dse_reset(cryp);
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if (err) {
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dev_err(cryp->dev, "Failed to reset DFE and DSE.\n");
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return err;
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}
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mtk_dfe_dse_buf_setup(cryp, &cap);
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/* Enable the 4 rings for the packet engines. */
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mtk_desc_ring_link(cryp, 0xf);
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for (i = 0; i < MTK_RING_MAX; i++) {
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mtk_cmd_desc_ring_setup(cryp, i, &cap);
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mtk_res_desc_ring_setup(cryp, i, &cap);
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}
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writel(MTK_PE_TK_LOC_AVL | MTK_PE_PROC_HELD | MTK_PE_TK_TIMEOUT_EN,
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cryp->base + PE_TOKEN_CTRL_STAT);
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/* Clear all pending interrupts */
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writel(MTK_AIC_G_CLR, cryp->base + AIC_G_ACK);
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writel(MTK_PE_INPUT_DMA_ERR | MTK_PE_OUTPUT_DMA_ERR |
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MTK_PE_PKT_PORC_ERR | MTK_PE_PKT_TIMEOUT |
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MTK_PE_FATAL_ERR | MTK_PE_INPUT_DMA_ERR_EN |
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MTK_PE_OUTPUT_DMA_ERR_EN | MTK_PE_PKT_PORC_ERR_EN |
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MTK_PE_PKT_TIMEOUT_EN | MTK_PE_FATAL_ERR_EN |
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MTK_PE_INT_OUT_EN,
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cryp->base + PE_INTERRUPT_CTRL_STAT);
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return 0;
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}
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static int mtk_aic_cap_check(struct mtk_cryp *cryp, int hw)
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{
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u32 val;
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if (hw == MTK_RING_MAX)
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val = readl(cryp->base + AIC_G_VERSION);
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else
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val = readl(cryp->base + AIC_VERSION(hw));
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val &= MTK_AIC_VER_MSK;
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if (val != MTK_AIC_VER11 && val != MTK_AIC_VER12)
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return -ENXIO;
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if (hw == MTK_RING_MAX)
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val = readl(cryp->base + AIC_G_OPTIONS);
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else
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val = readl(cryp->base + AIC_OPTIONS(hw));
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val &= MTK_AIC_INT_MSK;
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if (!val || val > 32)
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return -ENXIO;
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return 0;
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}
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static int mtk_aic_init(struct mtk_cryp *cryp, int hw)
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{
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int err;
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err = mtk_aic_cap_check(cryp, hw);
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if (err)
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return err;
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/* Disable all interrupts and set initial configuration */
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if (hw == MTK_RING_MAX) {
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writel(0, cryp->base + AIC_G_ENABLE_CTRL);
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writel(0, cryp->base + AIC_G_POL_CTRL);
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writel(0, cryp->base + AIC_G_TYPE_CTRL);
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writel(0, cryp->base + AIC_G_ENABLE_SET);
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} else {
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writel(0, cryp->base + AIC_ENABLE_CTRL(hw));
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writel(0, cryp->base + AIC_POL_CTRL(hw));
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writel(0, cryp->base + AIC_TYPE_CTRL(hw));
|
|
writel(0, cryp->base + AIC_ENABLE_SET(hw));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_accelerator_init(struct mtk_cryp *cryp)
|
|
{
|
|
int i, err;
|
|
|
|
/* Initialize advanced interrupt controller(AIC) */
|
|
for (i = 0; i < MTK_IRQ_NUM; i++) {
|
|
err = mtk_aic_init(cryp, i);
|
|
if (err) {
|
|
dev_err(cryp->dev, "Failed to initialize AIC.\n");
|
|
return err;
|
|
}
|
|
}
|
|
|
|
/* Initialize packet engine */
|
|
err = mtk_packet_engine_setup(cryp);
|
|
if (err) {
|
|
dev_err(cryp->dev, "Failed to configure packet engine.\n");
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mtk_desc_dma_free(struct mtk_cryp *cryp)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < MTK_RING_MAX; i++) {
|
|
dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
|
|
cryp->ring[i]->res_base,
|
|
cryp->ring[i]->res_dma);
|
|
dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
|
|
cryp->ring[i]->cmd_base,
|
|
cryp->ring[i]->cmd_dma);
|
|
kfree(cryp->ring[i]);
|
|
}
|
|
}
|
|
|
|
static int mtk_desc_ring_alloc(struct mtk_cryp *cryp)
|
|
{
|
|
struct mtk_ring **ring = cryp->ring;
|
|
int i, err = ENOMEM;
|
|
|
|
for (i = 0; i < MTK_RING_MAX; i++) {
|
|
ring[i] = kzalloc(sizeof(**ring), GFP_KERNEL);
|
|
if (!ring[i])
|
|
goto err_cleanup;
|
|
|
|
ring[i]->cmd_base = dma_zalloc_coherent(cryp->dev,
|
|
MTK_DESC_RING_SZ,
|
|
&ring[i]->cmd_dma,
|
|
GFP_KERNEL);
|
|
if (!ring[i]->cmd_base)
|
|
goto err_cleanup;
|
|
|
|
ring[i]->res_base = dma_zalloc_coherent(cryp->dev,
|
|
MTK_DESC_RING_SZ,
|
|
&ring[i]->res_dma,
|
|
GFP_KERNEL);
|
|
if (!ring[i]->res_base)
|
|
goto err_cleanup;
|
|
|
|
ring[i]->cmd_next = ring[i]->cmd_base;
|
|
ring[i]->res_next = ring[i]->res_base;
|
|
}
|
|
return 0;
|
|
|
|
err_cleanup:
|
|
for (; i--; ) {
|
|
dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
|
|
ring[i]->res_base, ring[i]->res_dma);
|
|
dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
|
|
ring[i]->cmd_base, ring[i]->cmd_dma);
|
|
kfree(ring[i]);
|
|
}
|
|
return err;
|
|
}
|
|
|
|
static int mtk_crypto_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
struct mtk_cryp *cryp;
|
|
int i, err;
|
|
|
|
cryp = devm_kzalloc(&pdev->dev, sizeof(*cryp), GFP_KERNEL);
|
|
if (!cryp)
|
|
return -ENOMEM;
|
|
|
|
cryp->base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(cryp->base))
|
|
return PTR_ERR(cryp->base);
|
|
|
|
for (i = 0; i < MTK_IRQ_NUM; i++) {
|
|
cryp->irq[i] = platform_get_irq(pdev, i);
|
|
if (cryp->irq[i] < 0) {
|
|
dev_err(cryp->dev, "no IRQ:%d resource info\n", i);
|
|
return cryp->irq[i];
|
|
}
|
|
}
|
|
|
|
cryp->clk_cryp = devm_clk_get(&pdev->dev, "cryp");
|
|
if (IS_ERR(cryp->clk_cryp))
|
|
return -EPROBE_DEFER;
|
|
|
|
cryp->dev = &pdev->dev;
|
|
pm_runtime_enable(cryp->dev);
|
|
pm_runtime_get_sync(cryp->dev);
|
|
|
|
err = clk_prepare_enable(cryp->clk_cryp);
|
|
if (err)
|
|
goto err_clk_cryp;
|
|
|
|
/* Allocate four command/result descriptor rings */
|
|
err = mtk_desc_ring_alloc(cryp);
|
|
if (err) {
|
|
dev_err(cryp->dev, "Unable to allocate descriptor rings.\n");
|
|
goto err_resource;
|
|
}
|
|
|
|
/* Initialize hardware modules */
|
|
err = mtk_accelerator_init(cryp);
|
|
if (err) {
|
|
dev_err(cryp->dev, "Failed to initialize cryptographic engine.\n");
|
|
goto err_engine;
|
|
}
|
|
|
|
err = mtk_cipher_alg_register(cryp);
|
|
if (err) {
|
|
dev_err(cryp->dev, "Unable to register cipher algorithm.\n");
|
|
goto err_cipher;
|
|
}
|
|
|
|
err = mtk_hash_alg_register(cryp);
|
|
if (err) {
|
|
dev_err(cryp->dev, "Unable to register hash algorithm.\n");
|
|
goto err_hash;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, cryp);
|
|
return 0;
|
|
|
|
err_hash:
|
|
mtk_cipher_alg_release(cryp);
|
|
err_cipher:
|
|
mtk_dfe_dse_reset(cryp);
|
|
err_engine:
|
|
mtk_desc_dma_free(cryp);
|
|
err_resource:
|
|
clk_disable_unprepare(cryp->clk_cryp);
|
|
err_clk_cryp:
|
|
pm_runtime_put_sync(cryp->dev);
|
|
pm_runtime_disable(cryp->dev);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int mtk_crypto_remove(struct platform_device *pdev)
|
|
{
|
|
struct mtk_cryp *cryp = platform_get_drvdata(pdev);
|
|
|
|
mtk_hash_alg_release(cryp);
|
|
mtk_cipher_alg_release(cryp);
|
|
mtk_desc_dma_free(cryp);
|
|
|
|
clk_disable_unprepare(cryp->clk_cryp);
|
|
|
|
pm_runtime_put_sync(cryp->dev);
|
|
pm_runtime_disable(cryp->dev);
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id of_crypto_id[] = {
|
|
{ .compatible = "mediatek,eip97-crypto" },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, of_crypto_id);
|
|
|
|
static struct platform_driver mtk_crypto_driver = {
|
|
.probe = mtk_crypto_probe,
|
|
.remove = mtk_crypto_remove,
|
|
.driver = {
|
|
.name = "mtk-crypto",
|
|
.of_match_table = of_crypto_id,
|
|
},
|
|
};
|
|
module_platform_driver(mtk_crypto_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Ryder Lee <ryder.lee@mediatek.com>");
|
|
MODULE_DESCRIPTION("Cryptographic accelerator driver for EIP97");
|