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1b5ab8755e
Add an inv_llc_pol field to platform data to control the clock polarity. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Hans Verkuil <hans.verkuil@cisco.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
173 lines
4.6 KiB
C
173 lines
4.6 KiB
C
/*
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* adv7604 - Analog Devices ADV7604 video decoder driver
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*
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* Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
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*
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* This program is free software; you may redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#ifndef _ADV7604_
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#define _ADV7604_
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#include <linux/types.h>
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/* Analog input muxing modes (AFE register 0x02, [2:0]) */
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enum adv7604_ain_sel {
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ADV7604_AIN1_2_3_NC_SYNC_1_2 = 0,
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ADV7604_AIN4_5_6_NC_SYNC_2_1 = 1,
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ADV7604_AIN7_8_9_NC_SYNC_3_1 = 2,
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ADV7604_AIN10_11_12_NC_SYNC_4_1 = 3,
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ADV7604_AIN9_4_5_6_SYNC_2_1 = 4,
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};
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/*
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* Bus rotation and reordering. This is used to specify component reordering on
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* the board and describes the components order on the bus when the ADV7604
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* outputs RGB.
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*/
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enum adv7604_bus_order {
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ADV7604_BUS_ORDER_RGB, /* No operation */
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ADV7604_BUS_ORDER_GRB, /* Swap 1-2 */
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ADV7604_BUS_ORDER_RBG, /* Swap 2-3 */
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ADV7604_BUS_ORDER_BGR, /* Swap 1-3 */
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ADV7604_BUS_ORDER_BRG, /* Rotate right */
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ADV7604_BUS_ORDER_GBR, /* Rotate left */
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};
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/* Input Color Space (IO register 0x02, [7:4]) */
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enum adv7604_inp_color_space {
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ADV7604_INP_COLOR_SPACE_LIM_RGB = 0,
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ADV7604_INP_COLOR_SPACE_FULL_RGB = 1,
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ADV7604_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
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ADV7604_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
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ADV7604_INP_COLOR_SPACE_XVYCC_601 = 4,
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ADV7604_INP_COLOR_SPACE_XVYCC_709 = 5,
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ADV7604_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
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ADV7604_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
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ADV7604_INP_COLOR_SPACE_AUTO = 0xf,
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};
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/* Select output format (IO register 0x03, [4:2]) */
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enum adv7604_op_format_mode_sel {
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ADV7604_OP_FORMAT_MODE0 = 0x00,
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ADV7604_OP_FORMAT_MODE1 = 0x04,
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ADV7604_OP_FORMAT_MODE2 = 0x08,
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};
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enum adv7604_drive_strength {
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ADV7604_DR_STR_MEDIUM_LOW = 1,
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ADV7604_DR_STR_MEDIUM_HIGH = 2,
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ADV7604_DR_STR_HIGH = 3,
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};
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enum adv7604_int1_config {
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ADV7604_INT1_CONFIG_OPEN_DRAIN,
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ADV7604_INT1_CONFIG_ACTIVE_LOW,
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ADV7604_INT1_CONFIG_ACTIVE_HIGH,
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ADV7604_INT1_CONFIG_DISABLED,
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};
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enum adv7604_page {
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ADV7604_PAGE_IO,
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ADV7604_PAGE_AVLINK,
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ADV7604_PAGE_CEC,
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ADV7604_PAGE_INFOFRAME,
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ADV7604_PAGE_ESDP,
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ADV7604_PAGE_DPP,
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ADV7604_PAGE_AFE,
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ADV7604_PAGE_REP,
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ADV7604_PAGE_EDID,
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ADV7604_PAGE_HDMI,
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ADV7604_PAGE_TEST,
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ADV7604_PAGE_CP,
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ADV7604_PAGE_VDP,
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ADV7604_PAGE_MAX,
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};
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/* Platform dependent definition */
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struct adv7604_platform_data {
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/* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
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unsigned disable_pwrdnb:1;
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/* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
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unsigned disable_cable_det_rst:1;
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int default_input;
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/* Analog input muxing mode */
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enum adv7604_ain_sel ain_sel;
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/* Bus rotation and reordering */
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enum adv7604_bus_order bus_order;
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/* Select output format mode */
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enum adv7604_op_format_mode_sel op_format_mode_sel;
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/* Configuration of the INT1 pin */
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enum adv7604_int1_config int1_config;
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/* IO register 0x02 */
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unsigned alt_gamma:1;
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unsigned op_656_range:1;
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unsigned alt_data_sat:1;
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/* IO register 0x05 */
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unsigned blank_data:1;
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unsigned insert_av_codes:1;
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unsigned replicate_av_codes:1;
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/* IO register 0x06 */
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unsigned inv_vs_pol:1;
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unsigned inv_hs_pol:1;
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unsigned inv_llc_pol:1;
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/* IO register 0x14 */
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enum adv7604_drive_strength dr_str_data;
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enum adv7604_drive_strength dr_str_clk;
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enum adv7604_drive_strength dr_str_sync;
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/* IO register 0x30 */
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unsigned output_bus_lsb_to_msb:1;
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/* Free run */
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unsigned hdmi_free_run_mode;
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/* i2c addresses: 0 == use default */
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u8 i2c_addresses[ADV7604_PAGE_MAX];
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};
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enum adv7604_pad {
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ADV7604_PAD_HDMI_PORT_A = 0,
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ADV7604_PAD_HDMI_PORT_B = 1,
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ADV7604_PAD_HDMI_PORT_C = 2,
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ADV7604_PAD_HDMI_PORT_D = 3,
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ADV7604_PAD_VGA_RGB = 4,
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ADV7604_PAD_VGA_COMP = 5,
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/* The source pad is either 1 (ADV7611) or 6 (ADV7604) */
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ADV7604_PAD_SOURCE = 6,
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ADV7611_PAD_SOURCE = 1,
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ADV7604_PAD_MAX = 7,
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};
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#define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000)
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#define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001)
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#define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002)
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/* notify events */
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#define ADV7604_HOTPLUG 1
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#define ADV7604_FMT_CHANGE 2
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#endif
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