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4bd66cfde5
Implement irq_eoi to allow the GIC irq chip flow controller to be changed to fasteoi. Signed-off-by: Colin Cross <ccross@android.com>
135 lines
3.1 KiB
C
135 lines
3.1 KiB
C
/*
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* Copyright (C) 2011 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@android.com>
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*
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* Copyright (C) 2010, NVIDIA Corporation
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/hardware/gic.h>
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#include <mach/iomap.h>
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#include "board.h"
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#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE)
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#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE)
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#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
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#define ICTLR_CPU_IEP_VFIQ 0x08
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#define ICTLR_CPU_IEP_FIR 0x14
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#define ICTLR_CPU_IEP_FIR_SET 0x18
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#define ICTLR_CPU_IEP_FIR_CLR 0x1c
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#define ICTLR_CPU_IER 0x20
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#define ICTLR_CPU_IER_SET 0x24
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#define ICTLR_CPU_IER_CLR 0x28
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#define ICTLR_CPU_IEP_CLASS 0x2C
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#define ICTLR_COP_IER 0x30
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#define ICTLR_COP_IER_SET 0x34
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#define ICTLR_COP_IER_CLR 0x38
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#define ICTLR_COP_IEP_CLASS 0x3c
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#define NUM_ICTLRS 4
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#define FIRST_LEGACY_IRQ 32
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static void __iomem *ictlr_reg_base[] = {
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IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
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IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
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IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
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IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
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};
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static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
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{
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void __iomem *base;
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u32 mask;
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BUG_ON(irq < FIRST_LEGACY_IRQ ||
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irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32);
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base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
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mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
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__raw_writel(mask, base + reg);
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}
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static void tegra_mask(struct irq_data *d)
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{
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if (d->irq < FIRST_LEGACY_IRQ)
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return;
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tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR);
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}
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static void tegra_unmask(struct irq_data *d)
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{
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if (d->irq < FIRST_LEGACY_IRQ)
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return;
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tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET);
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}
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static void tegra_ack(struct irq_data *d)
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{
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if (d->irq < FIRST_LEGACY_IRQ)
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return;
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tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
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}
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static void tegra_eoi(struct irq_data *d)
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{
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if (d->irq < FIRST_LEGACY_IRQ)
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return;
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tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
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}
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static int tegra_retrigger(struct irq_data *d)
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{
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if (d->irq < FIRST_LEGACY_IRQ)
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return 0;
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tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET);
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return 1;
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}
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void __init tegra_init_irq(void)
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{
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int i;
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for (i = 0; i < NUM_ICTLRS; i++) {
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void __iomem *ictlr = ictlr_reg_base[i];
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writel(~0, ictlr + ICTLR_CPU_IER_CLR);
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writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
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}
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gic_arch_extn.irq_ack = tegra_ack;
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gic_arch_extn.irq_eoi = tegra_eoi;
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gic_arch_extn.irq_mask = tegra_mask;
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gic_arch_extn.irq_unmask = tegra_unmask;
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gic_arch_extn.irq_retrigger = tegra_retrigger;
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gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
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IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
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}
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