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6ac77e469e
The GIC register accesses today make use of readl()/writel() which prove to be very expensive when used along with mandatory barriers. This mandatory barriers also introduces an un-necessary and expensive l2x0_sync() operation. On Cortex-A9 MP cores, GIC IO accesses from CPU are direct and doesn't go through L2X0 write buffer. A DSB before writel_relaxed() in gic_raise_softirq() is added to be compliant with the Barrier Litmus document - the mailbox scenario. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> |
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| .. | ||
| dmabounce.c | ||
| gic.c | ||
| icst.c | ||
| it8152.c | ||
| Kconfig | ||
| locomo.c | ||
| Makefile | ||
| pl330.c | ||
| sa1111.c | ||
| scoop.c | ||
| sharpsl_param.c | ||
| time-acorn.c | ||
| timer-sp.c | ||
| uengine.c | ||
| via82c505.c | ||
| vic.c | ||