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https://github.com/edk2-porting/linux-next.git
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dbf6719a4a
The KSZ9031 is used on the i.MX6 based Data Modul eDM-QMX6 board. It needs the same fixup to the rx/tx delays as other i.MX6 boards. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
419 lines
9.1 KiB
C
419 lines
9.1 KiB
C
/*
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* Copyright 2011-2013 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clocksource.h>
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#include <linux/cpu.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/opp.h>
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#include <linux/phy.h>
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#include <linux/reboot.h>
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#include <linux/regmap.h>
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#include <linux/micrel_phy.h>
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#include <linux/mfd/syscon.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/system_misc.h>
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#include "common.h"
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#include "cpuidle.h"
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#include "hardware.h"
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static u32 chip_revision;
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int imx6q_revision(void)
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{
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return chip_revision;
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}
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static void __init imx6q_init_revision(void)
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{
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u32 rev = imx_anatop_get_digprog();
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switch (rev & 0xff) {
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case 0:
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chip_revision = IMX_CHIP_REVISION_1_0;
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break;
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case 1:
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chip_revision = IMX_CHIP_REVISION_1_1;
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break;
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case 2:
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chip_revision = IMX_CHIP_REVISION_1_2;
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break;
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default:
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chip_revision = IMX_CHIP_REVISION_UNKNOWN;
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}
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mxc_set_cpu_type(rev >> 16 & 0xff);
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}
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static void imx6q_restart(enum reboot_mode mode, const char *cmd)
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{
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struct device_node *np;
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void __iomem *wdog_base;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
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wdog_base = of_iomap(np, 0);
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if (!wdog_base)
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goto soft;
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imx_src_prepare_restart();
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/* enable wdog */
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writew_relaxed(1 << 2, wdog_base);
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/* write twice to ensure the request will not get ignored */
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writew_relaxed(1 << 2, wdog_base);
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/* wait for reset to assert ... */
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mdelay(500);
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pr_err("Watchdog reset failed to assert reset\n");
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/* delay to allow the serial port to show the message */
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mdelay(50);
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soft:
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/* we'll take a jump through zero as a poor second */
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soft_restart(0);
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}
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/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
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static int ksz9021rn_phy_fixup(struct phy_device *phydev)
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{
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if (IS_BUILTIN(CONFIG_PHYLIB)) {
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/* min rx data delay */
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phy_write(phydev, 0x0b, 0x8105);
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phy_write(phydev, 0x0c, 0x0000);
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/* max rx/tx clock delay, min rx/tx control delay */
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phy_write(phydev, 0x0b, 0x8104);
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phy_write(phydev, 0x0c, 0xf0f0);
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phy_write(phydev, 0x0b, 0x104);
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}
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return 0;
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}
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static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
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{
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phy_write(dev, 0x0d, device);
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phy_write(dev, 0x0e, reg);
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phy_write(dev, 0x0d, (1 << 14) | device);
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phy_write(dev, 0x0e, val);
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}
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static int ksz9031rn_phy_fixup(struct phy_device *dev)
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{
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/*
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* min rx data delay, max rx/tx clock delay,
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* min rx/tx control delay
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*/
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mmd_write_reg(dev, 2, 4, 0);
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mmd_write_reg(dev, 2, 5, 0);
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mmd_write_reg(dev, 2, 8, 0x003ff);
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return 0;
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}
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static int ar8031_phy_fixup(struct phy_device *dev)
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{
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u16 val;
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/* To enable AR8031 output a 125MHz clk from CLK_25M */
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phy_write(dev, 0xd, 0x7);
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phy_write(dev, 0xe, 0x8016);
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phy_write(dev, 0xd, 0x4007);
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val = phy_read(dev, 0xe);
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val &= 0xffe3;
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val |= 0x18;
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phy_write(dev, 0xe, val);
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/* introduce tx clock delay */
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phy_write(dev, 0x1d, 0x5);
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val = phy_read(dev, 0x1e);
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val |= 0x0100;
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phy_write(dev, 0x1e, val);
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return 0;
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}
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static void __init imx6q_sabrelite_cko1_setup(void)
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{
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struct clk *cko1_sel, *ahb, *cko1;
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unsigned long rate;
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cko1_sel = clk_get_sys(NULL, "cko1_sel");
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ahb = clk_get_sys(NULL, "ahb");
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cko1 = clk_get_sys(NULL, "cko1");
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if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
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pr_err("cko1 setup failed!\n");
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goto put_clk;
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}
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clk_set_parent(cko1_sel, ahb);
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rate = clk_round_rate(cko1, 16000000);
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clk_set_rate(cko1, rate);
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put_clk:
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if (!IS_ERR(cko1_sel))
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clk_put(cko1_sel);
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if (!IS_ERR(ahb))
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clk_put(ahb);
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if (!IS_ERR(cko1))
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clk_put(cko1);
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}
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#define PHY_ID_AR8031 0x004dd074
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static void __init imx6q_enet_phy_init(void)
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{
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if (IS_BUILTIN(CONFIG_PHYLIB)) {
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phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
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ksz9021rn_phy_fixup);
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phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
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ksz9031rn_phy_fixup);
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phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
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ar8031_phy_fixup);
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}
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}
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static void __init imx6q_sabresd_cko1_setup(void)
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{
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struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
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unsigned long rate;
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cko1_sel = clk_get_sys(NULL, "cko1_sel");
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pll4 = clk_get_sys(NULL, "pll4_audio");
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pll4_post = clk_get_sys(NULL, "pll4_post_div");
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cko1 = clk_get_sys(NULL, "cko1");
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if (IS_ERR(cko1_sel) || IS_ERR(pll4)
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|| IS_ERR(pll4_post) || IS_ERR(cko1)) {
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pr_err("cko1 setup failed!\n");
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goto put_clk;
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}
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/*
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* Setting pll4 at 768MHz (24MHz * 32)
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* So its child clock can get 24MHz easily
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*/
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clk_set_rate(pll4, 768000000);
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clk_set_parent(cko1_sel, pll4_post);
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rate = clk_round_rate(cko1, 24000000);
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clk_set_rate(cko1, rate);
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put_clk:
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if (!IS_ERR(cko1_sel))
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clk_put(cko1_sel);
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if (!IS_ERR(pll4_post))
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clk_put(pll4_post);
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if (!IS_ERR(pll4))
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clk_put(pll4);
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if (!IS_ERR(cko1))
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clk_put(cko1);
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}
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static void __init imx6q_sabresd_init(void)
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{
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imx6q_sabresd_cko1_setup();
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}
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static void __init imx6q_1588_init(void)
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{
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struct regmap *gpr;
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gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
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if (!IS_ERR(gpr))
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regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
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else
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pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
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}
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static void __init imx6q_usb_init(void)
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{
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imx_anatop_usb_chrg_detect_disable();
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}
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static void __init imx6q_init_machine(void)
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{
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if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
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imx6q_sabrelite_cko1_setup();
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else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
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of_machine_is_compatible("fsl,imx6dl-sabresd"))
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imx6q_sabresd_init();
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imx6q_enet_phy_init();
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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imx_anatop_init();
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imx6q_pm_init();
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imx6q_usb_init();
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imx6q_1588_init();
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}
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#define OCOTP_CFG3 0x440
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#define OCOTP_CFG3_SPEED_SHIFT 16
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#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
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static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
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{
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struct device_node *np;
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void __iomem *base;
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u32 val;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
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if (!np) {
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pr_warn("failed to find ocotp node\n");
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return;
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}
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base = of_iomap(np, 0);
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if (!base) {
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pr_warn("failed to map ocotp\n");
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goto put_node;
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}
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val = readl_relaxed(base + OCOTP_CFG3);
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val >>= OCOTP_CFG3_SPEED_SHIFT;
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if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
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if (opp_disable(cpu_dev, 1200000000))
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pr_warn("failed to disable 1.2 GHz OPP\n");
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put_node:
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of_node_put(np);
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}
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static void __init imx6q_opp_init(struct device *cpu_dev)
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{
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struct device_node *np;
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np = of_find_node_by_path("/cpus/cpu@0");
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if (!np) {
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pr_warn("failed to find cpu0 node\n");
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return;
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}
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cpu_dev->of_node = np;
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if (of_init_opp_table(cpu_dev)) {
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pr_warn("failed to init OPP table\n");
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goto put_node;
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}
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imx6q_opp_check_1p2ghz(cpu_dev);
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put_node:
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of_node_put(np);
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}
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static struct platform_device imx6q_cpufreq_pdev = {
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.name = "imx6q-cpufreq",
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};
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static void __init imx6q_init_late(void)
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{
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/*
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* WAIT mode is broken on TO 1.0 and 1.1, so there is no point
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* to run cpuidle on them.
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*/
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if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
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imx6q_cpuidle_init();
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if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
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imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
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platform_device_register(&imx6q_cpufreq_pdev);
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}
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}
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static void __init imx6q_map_io(void)
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{
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debug_ll_io_init();
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imx_scu_map_io();
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}
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#ifdef CONFIG_CACHE_L2X0
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static void __init imx6q_init_l2cache(void)
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{
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void __iomem *l2x0_base;
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struct device_node *np;
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unsigned int val;
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np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
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if (!np)
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goto out;
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l2x0_base = of_iomap(np, 0);
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if (!l2x0_base) {
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of_node_put(np);
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goto out;
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}
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/* Configure the L2 PREFETCH and POWER registers */
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val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
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val |= 0x70800000;
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writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
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val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
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writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
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iounmap(l2x0_base);
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of_node_put(np);
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out:
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l2x0_of_init(0, ~0UL);
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}
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#else
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static inline void imx6q_init_l2cache(void) {}
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#endif
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static void __init imx6q_init_irq(void)
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{
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imx6q_init_revision();
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imx6q_init_l2cache();
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imx_src_init();
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imx_gpc_init();
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irqchip_init();
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}
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static void __init imx6q_timer_init(void)
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{
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of_clk_init(NULL);
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clocksource_of_init();
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imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
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imx6q_revision());
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}
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static const char *imx6q_dt_compat[] __initdata = {
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"fsl,imx6dl",
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"fsl,imx6q",
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NULL,
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};
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DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
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.smp = smp_ops(imx_smp_ops),
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.map_io = imx6q_map_io,
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.init_irq = imx6q_init_irq,
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.init_time = imx6q_timer_init,
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.init_machine = imx6q_init_machine,
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.init_late = imx6q_init_late,
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.dt_compat = imx6q_dt_compat,
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.restart = imx6q_restart,
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MACHINE_END
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