mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-29 23:53:55 +08:00
6ab3d5624e
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
508 lines
16 KiB
C
508 lines
16 KiB
C
/*
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* linux/drivers/video/cyber2000fb.h
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*
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* Copyright (C) 1998-2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Integraphics Cyber2000 frame buffer device
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*/
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/*
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* Internal CyberPro sizes and offsets.
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*/
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#define MMIO_OFFSET 0x00800000
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#define MMIO_SIZE 0x000c0000
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#define NR_PALETTE 256
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#if defined(DEBUG) && defined(CONFIG_DEBUG_LL)
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static void debug_printf(char *fmt, ...)
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{
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extern void printascii(const char *);
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char buffer[128];
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va_list ap;
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va_start(ap, fmt);
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vsprintf(buffer, fmt, ap);
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va_end(ap);
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printascii(buffer);
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}
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#else
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#define debug_printf(x...) do { } while (0)
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#endif
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#define RAMDAC_RAMPWRDN 0x01
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#define RAMDAC_DAC8BIT 0x02
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#define RAMDAC_VREFEN 0x04
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#define RAMDAC_BYPASS 0x10
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#define RAMDAC_DACPWRDN 0x40
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#define EXT_CRT_VRTOFL 0x11
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#define EXT_CRT_VRTOFL_LINECOMP10 0x10
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#define EXT_CRT_VRTOFL_INTERLACE 0x20
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#define EXT_CRT_IRQ 0x12
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#define EXT_CRT_IRQ_ENABLE 0x01
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#define EXT_CRT_IRQ_ACT_HIGH 0x04
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#define EXT_CRT_TEST 0x13
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#define EXT_SYNC_CTL 0x16
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#define EXT_SYNC_CTL_HS_NORMAL 0x00
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#define EXT_SYNC_CTL_HS_0 0x01
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#define EXT_SYNC_CTL_HS_1 0x02
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#define EXT_SYNC_CTL_HS_HSVS 0x03
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#define EXT_SYNC_CTL_VS_NORMAL 0x00
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#define EXT_SYNC_CTL_VS_0 0x04
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#define EXT_SYNC_CTL_VS_1 0x08
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#define EXT_SYNC_CTL_VS_COMP 0x0c
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#define EXT_BUS_CTL 0x30
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#define EXT_BUS_CTL_LIN_1MB 0x00
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#define EXT_BUS_CTL_LIN_2MB 0x01
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#define EXT_BUS_CTL_LIN_4MB 0x02
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#define EXT_BUS_CTL_ZEROWAIT 0x04
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#define EXT_BUS_CTL_PCIBURST_WRITE 0x20
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#define EXT_BUS_CTL_PCIBURST_READ 0x80 /* CyberPro 5000 only */
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#define EXT_SEG_WRITE_PTR 0x31
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#define EXT_SEG_READ_PTR 0x32
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#define EXT_BIU_MISC 0x33
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#define EXT_BIU_MISC_LIN_ENABLE 0x01
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#define EXT_BIU_MISC_COP_ENABLE 0x04
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#define EXT_BIU_MISC_COP_BFC 0x08
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#define EXT_FUNC_CTL 0x3c
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#define EXT_FUNC_CTL_EXTREGENBL 0x80 /* enable access to 0xbcxxx */
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#define PCI_BM_CTL 0x3e
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#define PCI_BM_CTL_ENABLE 0x01 /* enable bus-master */
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#define PCI_BM_CTL_BURST 0x02 /* enable burst */
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#define PCI_BM_CTL_BACK2BACK 0x04 /* enable back to back */
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#define PCI_BM_CTL_DUMMY 0x08 /* insert dummy cycle */
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#define X_V2_VID_MEM_START 0x40
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#define X_V2_VID_SRC_WIDTH 0x43
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#define X_V2_X_START 0x45
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#define X_V2_X_END 0x47
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#define X_V2_Y_START 0x49
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#define X_V2_Y_END 0x4b
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#define X_V2_VID_SRC_WIN_WIDTH 0x4d
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#define Y_V2_DDA_X_INC 0x43
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#define Y_V2_DDA_Y_INC 0x47
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#define Y_V2_VID_FIFO_CTL 0x49
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#define Y_V2_VID_FMT 0x4b
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#define Y_V2_VID_DISP_CTL1 0x4c
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#define Y_V2_VID_FIFO_CTL1 0x4d
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#define J_X2_VID_MEM_START 0x40
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#define J_X2_VID_SRC_WIDTH 0x43
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#define J_X2_X_START 0x47
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#define J_X2_X_END 0x49
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#define J_X2_Y_START 0x4b
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#define J_X2_Y_END 0x4d
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#define J_X2_VID_SRC_WIN_WIDTH 0x4f
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#define K_X2_DDA_X_INIT 0x40
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#define K_X2_DDA_X_INC 0x42
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#define K_X2_DDA_Y_INIT 0x44
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#define K_X2_DDA_Y_INC 0x46
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#define K_X2_VID_FMT 0x48
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#define K_X2_VID_DISP_CTL1 0x49
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#define K_CAP_X2_CTL1 0x49
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#define CURS_H_START 0x50
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#define CURS_H_PRESET 0x52
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#define CURS_V_START 0x53
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#define CURS_V_PRESET 0x55
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#define CURS_CTL 0x56
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#define EXT_ATTRIB_CTL 0x57
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#define EXT_ATTRIB_CTL_EXT 0x01
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#define EXT_OVERSCAN_RED 0x58
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#define EXT_OVERSCAN_GREEN 0x59
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#define EXT_OVERSCAN_BLUE 0x5a
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#define CAP_X_START 0x60
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#define CAP_X_END 0x62
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#define CAP_Y_START 0x64
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#define CAP_Y_END 0x66
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#define CAP_DDA_X_INIT 0x68
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#define CAP_DDA_X_INC 0x6a
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#define CAP_DDA_Y_INIT 0x6c
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#define CAP_DDA_Y_INC 0x6e
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#define EXT_MEM_CTL0 0x70
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#define EXT_MEM_CTL0_7CLK 0x01
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#define EXT_MEM_CTL0_RAS_1 0x02
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#define EXT_MEM_CTL0_RAS2CAS_1 0x04
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#define EXT_MEM_CTL0_MULTCAS 0x08
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#define EXT_MEM_CTL0_ASYM 0x10
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#define EXT_MEM_CTL0_CAS1ON 0x20
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#define EXT_MEM_CTL0_FIFOFLUSH 0x40
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#define EXT_MEM_CTL0_SEQRESET 0x80
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#define EXT_MEM_CTL1 0x71
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#define EXT_MEM_CTL1_PAR 0x00
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#define EXT_MEM_CTL1_SERPAR 0x01
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#define EXT_MEM_CTL1_SER 0x03
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#define EXT_MEM_CTL1_SYNC 0x04
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#define EXT_MEM_CTL1_VRAM 0x08
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#define EXT_MEM_CTL1_4K_REFRESH 0x10
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#define EXT_MEM_CTL1_256Kx4 0x00
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#define EXT_MEM_CTL1_512Kx8 0x40
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#define EXT_MEM_CTL1_1Mx16 0x60
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#define EXT_MEM_CTL2 0x72
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#define MEM_CTL2_SIZE_1MB 0x00
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#define MEM_CTL2_SIZE_2MB 0x01
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#define MEM_CTL2_SIZE_4MB 0x02
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#define MEM_CTL2_SIZE_MASK 0x03
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#define MEM_CTL2_64BIT 0x04
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#define EXT_HIDDEN_CTL1 0x73
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#define EXT_FIFO_CTL 0x74
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#define EXT_SEQ_MISC 0x77
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#define EXT_SEQ_MISC_8 0x01
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#define EXT_SEQ_MISC_16_RGB565 0x02
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#define EXT_SEQ_MISC_32 0x03
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#define EXT_SEQ_MISC_24_RGB888 0x04
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#define EXT_SEQ_MISC_16_RGB555 0x06
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#define EXT_SEQ_MISC_8_RGB332 0x09
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#define EXT_SEQ_MISC_16_RGB444 0x0a
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#define EXT_HIDDEN_CTL4 0x7a
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#define CURS_MEM_START 0x7e /* bits 23..12 */
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#define CAP_PIP_X_START 0x80
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#define CAP_PIP_X_END 0x82
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#define CAP_PIP_Y_START 0x84
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#define CAP_PIP_Y_END 0x86
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#define EXT_CAP_CTL1 0x88
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#define EXT_CAP_CTL2 0x89
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#define EXT_CAP_CTL2_ODDFRAMEIRQ 0x01
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#define EXT_CAP_CTL2_ANYFRAMEIRQ 0x02
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#define BM_CTRL0 0x9c
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#define BM_CTRL1 0x9d
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#define EXT_CAP_MODE1 0xa4
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#define EXT_CAP_MODE1_8BIT 0x01 /* enable 8bit capture mode */
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#define EXT_CAP_MODE1_CCIR656 0x02 /* CCIR656 mode */
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#define EXT_CAP_MODE1_IGNOREVGT 0x04 /* ignore VGT */
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#define EXT_CAP_MODE1_ALTFIFO 0x10 /* use alternate FIFO for capture */
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#define EXT_CAP_MODE1_SWAPUV 0x20 /* swap UV bytes */
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#define EXT_CAP_MODE1_MIRRORY 0x40 /* mirror vertically */
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#define EXT_CAP_MODE1_MIRRORX 0x80 /* mirror horizontally */
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#define EXT_CAP_MODE2 0xa5
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#define EXT_CAP_MODE2_CCIRINVOE 0x01
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#define EXT_CAP_MODE2_CCIRINVVGT 0x02
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#define EXT_CAP_MODE2_CCIRINVHGT 0x04
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#define EXT_CAP_MODE2_CCIRINVDG 0x08
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#define EXT_CAP_MODE2_DATEND 0x10
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#define EXT_CAP_MODE2_CCIRDGH 0x20
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#define EXT_CAP_MODE2_FIXSONY 0x40
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#define EXT_CAP_MODE2_SYNCFREEZE 0x80
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#define EXT_TV_CTL 0xae
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#define EXT_DCLK_MULT 0xb0
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#define EXT_DCLK_DIV 0xb1
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#define EXT_DCLK_DIV_VFSEL 0x20
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#define EXT_MCLK_MULT 0xb2
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#define EXT_MCLK_DIV 0xb3
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#define EXT_LATCH1 0xb5
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#define EXT_LATCH1_VAFC_EN 0x01 /* enable VAFC */
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#define EXT_FEATURE 0xb7
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#define EXT_FEATURE_BUS_MASK 0x07 /* host bus mask */
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#define EXT_FEATURE_BUS_PCI 0x00
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#define EXT_FEATURE_BUS_VL_STD 0x04
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#define EXT_FEATURE_BUS_VL_LINEAR 0x05
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#define EXT_FEATURE_1682 0x20 /* IGS 1682 compatibility */
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#define EXT_LATCH2 0xb6
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#define EXT_LATCH2_I2C_CLKEN 0x10
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#define EXT_LATCH2_I2C_CLK 0x20
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#define EXT_LATCH2_I2C_DATEN 0x40
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#define EXT_LATCH2_I2C_DAT 0x80
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#define EXT_XT_CTL 0xbe
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#define EXT_XT_CAP16 0x04
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#define EXT_XT_LINEARFB 0x08
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#define EXT_XT_PAL 0x10
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#define EXT_MEM_START 0xc0 /* ext start address 21 bits */
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#define HOR_PHASE_SHIFT 0xc2 /* high 3 bits */
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#define EXT_SRC_WIDTH 0xc3 /* ext offset phase 10 bits */
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#define EXT_SRC_HEIGHT 0xc4 /* high 6 bits */
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#define EXT_X_START 0xc5 /* ext->screen, 16 bits */
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#define EXT_X_END 0xc7 /* ext->screen, 16 bits */
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#define EXT_Y_START 0xc9 /* ext->screen, 16 bits */
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#define EXT_Y_END 0xcb /* ext->screen, 16 bits */
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#define EXT_SRC_WIN_WIDTH 0xcd /* 8 bits */
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#define EXT_COLOUR_COMPARE 0xce /* 24 bits */
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#define EXT_DDA_X_INIT 0xd1 /* ext->screen 16 bits */
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#define EXT_DDA_X_INC 0xd3 /* ext->screen 16 bits */
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#define EXT_DDA_Y_INIT 0xd5 /* ext->screen 16 bits */
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#define EXT_DDA_Y_INC 0xd7 /* ext->screen 16 bits */
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#define EXT_VID_FIFO_CTL 0xd9
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#define EXT_VID_FMT 0xdb
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#define EXT_VID_FMT_YUV422 0x00 /* formats - does this cause conversion? */
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#define EXT_VID_FMT_RGB555 0x01
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#define EXT_VID_FMT_RGB565 0x02
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#define EXT_VID_FMT_RGB888_24 0x03
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#define EXT_VID_FMT_RGB888_32 0x04
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#define EXT_VID_FMT_RGB8 0x05
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#define EXT_VID_FMT_RGB4444 0x06
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#define EXT_VID_FMT_RGB8T 0x07
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#define EXT_VID_FMT_DUP_PIX_ZOON 0x08 /* duplicate pixel zoom */
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#define EXT_VID_FMT_MOD_3RD_PIX 0x20 /* modify 3rd duplicated pixel */
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#define EXT_VID_FMT_DBL_H_PIX 0x40 /* double horiz pixels */
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#define EXT_VID_FMT_YUV128 0x80 /* YUV data offset by 128 */
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#define EXT_VID_DISP_CTL1 0xdc
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#define EXT_VID_DISP_CTL1_INTRAM 0x01 /* video pixels go to internal RAM */
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#define EXT_VID_DISP_CTL1_IGNORE_CCOMP 0x02 /* ignore colour compare registers */
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#define EXT_VID_DISP_CTL1_NOCLIP 0x04 /* do not clip to 16235,16240 */
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#define EXT_VID_DISP_CTL1_UV_AVG 0x08 /* U/V data is averaged */
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#define EXT_VID_DISP_CTL1_Y128 0x10 /* Y data offset by 128 (if YUV128 set) */
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#define EXT_VID_DISP_CTL1_VINTERPOL_OFF 0x20 /* disable vertical interpolation */
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#define EXT_VID_DISP_CTL1_FULL_WIN 0x40 /* video out window full */
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#define EXT_VID_DISP_CTL1_ENABLE_WINDOW 0x80 /* enable video window */
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#define EXT_VID_FIFO_CTL1 0xdd
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#define EXT_VID_FIFO_CTL1_OE_HIGH 0x02
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#define EXT_VID_FIFO_CTL1_INTERLEAVE 0x04 /* enable interleaved memory read */
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#define EXT_ROM_UCB4GH 0xe5
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#define EXT_ROM_UCB4GH_FREEZE 0x02 /* capture frozen */
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#define EXT_ROM_UCB4GH_ODDFRAME 0x04 /* 1 = odd frame captured */
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#define EXT_ROM_UCB4GH_1HL 0x08 /* first horizonal line after VGT falling edge */
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#define EXT_ROM_UCB4GH_ODD 0x10 /* odd frame indicator */
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#define EXT_ROM_UCB4GH_INTSTAT 0x20 /* video interrupt */
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#define VFAC_CTL1 0xe8
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#define VFAC_CTL1_CAPTURE 0x01 /* capture enable (only when VSYNC high)*/
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#define VFAC_CTL1_VFAC_ENABLE 0x02 /* vfac enable */
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#define VFAC_CTL1_FREEZE_CAPTURE 0x04 /* freeze capture */
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#define VFAC_CTL1_FREEZE_CAPTURE_SYNC 0x08 /* sync freeze capture */
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#define VFAC_CTL1_VALIDFRAME_SRC 0x10 /* select valid frame source */
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#define VFAC_CTL1_PHILIPS 0x40 /* select Philips mode */
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#define VFAC_CTL1_MODVINTERPOLCLK 0x80 /* modify vertical interpolation clocl */
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#define VFAC_CTL2 0xe9
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#define VFAC_CTL2_INVERT_VIDDATAVALID 0x01 /* invert video data valid */
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#define VFAC_CTL2_INVERT_GRAPHREADY 0x02 /* invert graphic ready output sig */
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#define VFAC_CTL2_INVERT_DATACLK 0x04 /* invert data clock signal */
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#define VFAC_CTL2_INVERT_HSYNC 0x08 /* invert hsync input */
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#define VFAC_CTL2_INVERT_VSYNC 0x10 /* invert vsync input */
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#define VFAC_CTL2_INVERT_FRAME 0x20 /* invert frame odd/even input */
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#define VFAC_CTL2_INVERT_BLANK 0x40 /* invert blank output */
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#define VFAC_CTL2_INVERT_OVSYNC 0x80 /* invert other vsync input */
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#define VFAC_CTL3 0xea
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#define VFAC_CTL3_CAP_LARGE_FIFO 0x01 /* large capture fifo */
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#define VFAC_CTL3_CAP_INTERLACE 0x02 /* capture odd and even fields */
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#define VFAC_CTL3_CAP_HOLD_4NS 0x00 /* hold capture data for 4ns */
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#define VFAC_CTL3_CAP_HOLD_2NS 0x04 /* hold capture data for 2ns */
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#define VFAC_CTL3_CAP_HOLD_6NS 0x08 /* hold capture data for 6ns */
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#define VFAC_CTL3_CAP_HOLD_0NS 0x0c /* hold capture data for 0ns */
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#define VFAC_CTL3_CHROMAKEY 0x20 /* capture data will be chromakeyed */
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#define VFAC_CTL3_CAP_IRQ 0x40 /* enable capture interrupt */
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#define CAP_MEM_START 0xeb /* 18 bits */
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#define CAP_MAP_WIDTH 0xed /* high 6 bits */
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#define CAP_PITCH 0xee /* 8 bits */
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#define CAP_CTL_MISC 0xef
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#define CAP_CTL_MISC_HDIV 0x01
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#define CAP_CTL_MISC_HDIV4 0x02
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#define CAP_CTL_MISC_ODDEVEN 0x04
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#define CAP_CTL_MISC_HSYNCDIV2 0x08
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#define CAP_CTL_MISC_SYNCTZHIGH 0x10
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#define CAP_CTL_MISC_SYNCTZOR 0x20
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#define CAP_CTL_MISC_DISPUSED 0x80
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#define REG_BANK 0xfa
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#define REG_BANK_X 0x00
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#define REG_BANK_Y 0x01
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#define REG_BANK_W 0x02
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#define REG_BANK_T 0x03
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#define REG_BANK_J 0x04
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#define REG_BANK_K 0x05
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/*
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* Bus-master
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*/
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#define BM_VID_ADDR_LOW 0xbc040
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#define BM_VID_ADDR_HIGH 0xbc044
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#define BM_ADDRESS_LOW 0xbc080
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#define BM_ADDRESS_HIGH 0xbc084
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#define BM_LENGTH 0xbc088
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#define BM_CONTROL 0xbc08c
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#define BM_CONTROL_ENABLE 0x01 /* enable transfer */
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#define BM_CONTROL_IRQEN 0x02 /* enable IRQ at end of transfer */
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#define BM_CONTROL_INIT 0x04 /* initialise status & count */
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#define BM_COUNT 0xbc090 /* read-only */
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/*
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* TV registers
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*/
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#define TV_VBLANK_EVEN_START 0xbe43c
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#define TV_VBLANK_EVEN_END 0xbe440
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#define TV_VBLANK_ODD_START 0xbe444
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#define TV_VBLANK_ODD_END 0xbe448
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#define TV_SYNC_YGAIN 0xbe44c
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#define TV_UV_GAIN 0xbe450
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#define TV_PED_UVDET 0xbe454
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#define TV_UV_BURST_AMP 0xbe458
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#define TV_HSYNC_START 0xbe45c
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#define TV_HSYNC_END 0xbe460
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#define TV_Y_DELAY1 0xbe464
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#define TV_Y_DELAY2 0xbe468
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#define TV_UV_DELAY1 0xbe46c
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#define TV_BURST_START 0xbe470
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#define TV_BURST_END 0xbe474
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#define TV_HBLANK_START 0xbe478
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#define TV_HBLANK_END 0xbe47c
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#define TV_PED_EVEN_START 0xbe480
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#define TV_PED_EVEN_END 0xbe484
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#define TV_PED_ODD_START 0xbe488
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#define TV_PED_ODD_END 0xbe48c
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|
#define TV_VSYNC_EVEN_START 0xbe490
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|
#define TV_VSYNC_EVEN_END 0xbe494
|
|
#define TV_VSYNC_ODD_START 0xbe498
|
|
#define TV_VSYNC_ODD_END 0xbe49c
|
|
#define TV_SCFL 0xbe4a0
|
|
#define TV_SCFH 0xbe4a4
|
|
#define TV_SCP 0xbe4a8
|
|
#define TV_DELAYBYPASS 0xbe4b4
|
|
#define TV_EQL_END 0xbe4bc
|
|
#define TV_SERR_START 0xbe4c0
|
|
#define TV_SERR_END 0xbe4c4
|
|
#define TV_CTL 0xbe4dc /* reflects a previous register- MVFCLR, MVPCLR etc P241*/
|
|
#define TV_VSYNC_VGA_HS 0xbe4e8
|
|
#define TV_FLICK_XMIN 0xbe514
|
|
#define TV_FLICK_XMAX 0xbe518
|
|
#define TV_FLICK_YMIN 0xbe51c
|
|
#define TV_FLICK_YMAX 0xbe520
|
|
|
|
/*
|
|
* Graphics Co-processor
|
|
*/
|
|
#define CO_REG_CONTROL 0xbf011
|
|
#define CO_CTRL_BUSY 0x80
|
|
#define CO_CTRL_CMDFULL 0x04
|
|
#define CO_CTRL_FIFOEMPTY 0x02
|
|
#define CO_CTRL_READY 0x01
|
|
|
|
#define CO_REG_SRC_WIDTH 0xbf018
|
|
#define CO_REG_PIXFMT 0xbf01c
|
|
#define CO_PIXFMT_32BPP 0x03
|
|
#define CO_PIXFMT_24BPP 0x02
|
|
#define CO_PIXFMT_16BPP 0x01
|
|
#define CO_PIXFMT_8BPP 0x00
|
|
|
|
#define CO_REG_FGMIX 0xbf048
|
|
#define CO_FG_MIX_ZERO 0x00
|
|
#define CO_FG_MIX_SRC_AND_DST 0x01
|
|
#define CO_FG_MIX_SRC_AND_NDST 0x02
|
|
#define CO_FG_MIX_SRC 0x03
|
|
#define CO_FG_MIX_NSRC_AND_DST 0x04
|
|
#define CO_FG_MIX_DST 0x05
|
|
#define CO_FG_MIX_SRC_XOR_DST 0x06
|
|
#define CO_FG_MIX_SRC_OR_DST 0x07
|
|
#define CO_FG_MIX_NSRC_AND_NDST 0x08
|
|
#define CO_FG_MIX_SRC_XOR_NDST 0x09
|
|
#define CO_FG_MIX_NDST 0x0a
|
|
#define CO_FG_MIX_SRC_OR_NDST 0x0b
|
|
#define CO_FG_MIX_NSRC 0x0c
|
|
#define CO_FG_MIX_NSRC_OR_DST 0x0d
|
|
#define CO_FG_MIX_NSRC_OR_NDST 0x0e
|
|
#define CO_FG_MIX_ONES 0x0f
|
|
|
|
#define CO_REG_FGCOLOUR 0xbf058
|
|
#define CO_REG_BGCOLOUR 0xbf05c
|
|
#define CO_REG_PIXWIDTH 0xbf060
|
|
#define CO_REG_PIXHEIGHT 0xbf062
|
|
#define CO_REG_X_PHASE 0xbf078
|
|
#define CO_REG_CMD_L 0xbf07c
|
|
#define CO_CMD_L_PATTERN_FGCOL 0x8000
|
|
#define CO_CMD_L_INC_LEFT 0x0004
|
|
#define CO_CMD_L_INC_UP 0x0002
|
|
|
|
#define CO_REG_CMD_H 0xbf07e
|
|
#define CO_CMD_H_BGSRCMAP 0x8000 /* otherwise bg colour */
|
|
#define CO_CMD_H_FGSRCMAP 0x2000 /* otherwise fg colour */
|
|
#define CO_CMD_H_BLITTER 0x0800
|
|
|
|
#define CO_REG_SRC1_PTR 0xbf170
|
|
#define CO_REG_SRC2_PTR 0xbf174
|
|
#define CO_REG_DEST_PTR 0xbf178
|
|
#define CO_REG_DEST_WIDTH 0xbf218
|
|
|
|
/*
|
|
* Private structure
|
|
*/
|
|
struct cfb_info;
|
|
|
|
struct cyberpro_info {
|
|
struct pci_dev *dev;
|
|
unsigned char __iomem *regs;
|
|
char __iomem *fb;
|
|
char dev_name[32];
|
|
unsigned int fb_size;
|
|
unsigned int chip_id;
|
|
|
|
/*
|
|
* The following is a pointer to be passed into the
|
|
* functions below. The modules outside the main
|
|
* cyber2000fb.c driver have no knowledge as to what
|
|
* is within this structure.
|
|
*/
|
|
struct cfb_info *info;
|
|
|
|
/*
|
|
* Use these to enable the BM or TV registers. In an SMP
|
|
* environment, these two function pointers should only be
|
|
* called from the module_init() or module_exit()
|
|
* functions.
|
|
*/
|
|
void (*enable_extregs)(struct cfb_info *);
|
|
void (*disable_extregs)(struct cfb_info *);
|
|
};
|
|
|
|
#define ID_IGA_1682 0
|
|
#define ID_CYBERPRO_2000 1
|
|
#define ID_CYBERPRO_2010 2
|
|
#define ID_CYBERPRO_5000 3
|
|
|
|
struct fb_var_screeninfo;
|
|
|
|
/*
|
|
* Note! Writing to the Cyber20x0 registers from an interrupt
|
|
* routine is definitely a bad idea atm.
|
|
*/
|
|
int cyber2000fb_attach(struct cyberpro_info *info, int idx);
|
|
void cyber2000fb_detach(int idx);
|
|
void cyber2000fb_enable_extregs(struct cfb_info *cfb);
|
|
void cyber2000fb_disable_extregs(struct cfb_info *cfb);
|
|
void cyber2000fb_get_fb_var(struct cfb_info *cfb, struct fb_var_screeninfo *var);
|