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Add the documenation for TSX Async Abort. Include the description of the issue, how to check the mitigation state, control the mitigation, guidance for system administrators. [ bp: Add proper SPDX tags, touch ups by Josh and me. ] Co-developed-by: Antonio Gomez Iglesias <antonio.gomez.iglesias@intel.com> Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: Antonio Gomez Iglesias <antonio.gomez.iglesias@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Mark Gross <mgross@linux.intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com>
118 lines
6.8 KiB
ReStructuredText
118 lines
6.8 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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TSX Async Abort (TAA) mitigation
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================================
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.. _tsx_async_abort:
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Overview
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--------
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TSX Async Abort (TAA) is a side channel attack on internal buffers in some
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Intel processors similar to Microachitectural Data Sampling (MDS). In this
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case certain loads may speculatively pass invalid data to dependent operations
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when an asynchronous abort condition is pending in a Transactional
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Synchronization Extensions (TSX) transaction. This includes loads with no
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fault or assist condition. Such loads may speculatively expose stale data from
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the same uarch data structures as in MDS, with same scope of exposure i.e.
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same-thread and cross-thread. This issue affects all current processors that
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support TSX.
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Mitigation strategy
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-------------------
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a) TSX disable - one of the mitigations is to disable TSX. A new MSR
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IA32_TSX_CTRL will be available in future and current processors after
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microcode update which can be used to disable TSX. In addition, it
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controls the enumeration of the TSX feature bits (RTM and HLE) in CPUID.
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b) Clear CPU buffers - similar to MDS, clearing the CPU buffers mitigates this
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vulnerability. More details on this approach can be found in
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:ref:`Documentation/admin-guide/hw-vuln/mds.rst <mds>`.
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Kernel internal mitigation modes
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--------------------------------
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============= ============================================================
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off Mitigation is disabled. Either the CPU is not affected or
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tsx_async_abort=off is supplied on the kernel command line.
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tsx disabled Mitigation is enabled. TSX feature is disabled by default at
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bootup on processors that support TSX control.
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verw Mitigation is enabled. CPU is affected and MD_CLEAR is
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advertised in CPUID.
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ucode needed Mitigation is enabled. CPU is affected and MD_CLEAR is not
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advertised in CPUID. That is mainly for virtualization
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scenarios where the host has the updated microcode but the
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hypervisor does not expose MD_CLEAR in CPUID. It's a best
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effort approach without guarantee.
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============= ============================================================
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If the CPU is affected and the "tsx_async_abort" kernel command line parameter is
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not provided then the kernel selects an appropriate mitigation depending on the
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status of RTM and MD_CLEAR CPUID bits.
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Below tables indicate the impact of tsx=on|off|auto cmdline options on state of
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TAA mitigation, VERW behavior and TSX feature for various combinations of
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MSR_IA32_ARCH_CAPABILITIES bits.
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1. "tsx=off"
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========= ========= ============ ============ ============== =================== ======================
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MSR_IA32_ARCH_CAPABILITIES bits Result with cmdline tsx=off
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---------------------------------- -------------------------------------------------------------------------
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TAA_NO MDS_NO TSX_CTRL_MSR TSX state VERW can clear TAA mitigation TAA mitigation
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after bootup CPU buffers tsx_async_abort=off tsx_async_abort=full
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========= ========= ============ ============ ============== =================== ======================
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0 0 0 HW default Yes Same as MDS Same as MDS
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0 0 1 Invalid case Invalid case Invalid case Invalid case
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0 1 0 HW default No Need ucode update Need ucode update
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0 1 1 Disabled Yes TSX disabled TSX disabled
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1 X 1 Disabled X None needed None needed
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========= ========= ============ ============ ============== =================== ======================
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2. "tsx=on"
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========= ========= ============ ============ ============== =================== ======================
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MSR_IA32_ARCH_CAPABILITIES bits Result with cmdline tsx=on
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---------------------------------- -------------------------------------------------------------------------
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TAA_NO MDS_NO TSX_CTRL_MSR TSX state VERW can clear TAA mitigation TAA mitigation
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after bootup CPU buffers tsx_async_abort=off tsx_async_abort=full
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========= ========= ============ ============ ============== =================== ======================
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0 0 0 HW default Yes Same as MDS Same as MDS
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0 0 1 Invalid case Invalid case Invalid case Invalid case
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0 1 0 HW default No Need ucode update Need ucode update
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0 1 1 Enabled Yes None Same as MDS
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1 X 1 Enabled X None needed None needed
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========= ========= ============ ============ ============== =================== ======================
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3. "tsx=auto"
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========= ========= ============ ============ ============== =================== ======================
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MSR_IA32_ARCH_CAPABILITIES bits Result with cmdline tsx=auto
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---------------------------------- -------------------------------------------------------------------------
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TAA_NO MDS_NO TSX_CTRL_MSR TSX state VERW can clear TAA mitigation TAA mitigation
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after bootup CPU buffers tsx_async_abort=off tsx_async_abort=full
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========= ========= ============ ============ ============== =================== ======================
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0 0 0 HW default Yes Same as MDS Same as MDS
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0 0 1 Invalid case Invalid case Invalid case Invalid case
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0 1 0 HW default No Need ucode update Need ucode update
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0 1 1 Disabled Yes TSX disabled TSX disabled
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1 X 1 Enabled X None needed None needed
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========= ========= ============ ============ ============== =================== ======================
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In the tables, TSX_CTRL_MSR is a new bit in MSR_IA32_ARCH_CAPABILITIES that
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indicates whether MSR_IA32_TSX_CTRL is supported.
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There are two control bits in IA32_TSX_CTRL MSR:
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Bit 0: When set it disables the Restricted Transactional Memory (RTM)
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sub-feature of TSX (will force all transactions to abort on the
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XBEGIN instruction).
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Bit 1: When set it disables the enumeration of the RTM and HLE feature
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(i.e. it will make CPUID(EAX=7).EBX{bit4} and
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CPUID(EAX=7).EBX{bit11} read as 0).
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