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0fa1f0609a
The orion watchdog is expecting to be passed the physcial address of the hardware, and will ioremap() it to give a virtual address it will use as the base address for the hardware. However, when creating the platform resource record, a virtual address was being used. Add the necassary #define's so we can pass the physical address as expected. Tested on Kirkwood and Orion5x. Cc: stable <stable@vger.kernel.org> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Olof Johansson <olof@lixom.net>
82 lines
2.2 KiB
C
82 lines
2.2 KiB
C
/*
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* arch/arm/mach-kirkwood/include/mach/bridge-regs.h
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*
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* Mbus-L to Mbus Bridge Registers
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_BRIDGE_REGS_H
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#define __ASM_ARCH_BRIDGE_REGS_H
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#include <mach/kirkwood.h>
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#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0100)
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#define CPU_CONFIG_ERROR_PROP 0x00000004
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#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
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#define CPU_RESET 0x00000002
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
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#define WDT_RESET_OUT_EN 0x00000002
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
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#define WDT_INT_REQ 0x0008
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
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#define IRQ_CAUSE_LOW_OFF 0x0000
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#define IRQ_MASK_LOW_OFF 0x0004
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#define IRQ_CAUSE_HIGH_OFF 0x0010
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#define IRQ_MASK_HIGH_OFF 0x0014
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
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#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300)
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#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
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#define L2_WRITETHROUGH 0x00000010
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#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c)
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#define CGC_BIT_GE0 (0)
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#define CGC_BIT_PEX0 (2)
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#define CGC_BIT_USB0 (3)
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#define CGC_BIT_SDIO (4)
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#define CGC_BIT_TSU (5)
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#define CGC_BIT_DUNIT (6)
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#define CGC_BIT_RUNIT (7)
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#define CGC_BIT_XOR0 (8)
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#define CGC_BIT_AUDIO (9)
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#define CGC_BIT_SATA0 (14)
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#define CGC_BIT_SATA1 (15)
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#define CGC_BIT_XOR1 (16)
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#define CGC_BIT_CRYPTO (17)
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#define CGC_BIT_PEX1 (18)
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#define CGC_BIT_GE1 (19)
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#define CGC_BIT_TDM (20)
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#define CGC_GE0 (1 << 0)
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#define CGC_PEX0 (1 << 2)
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#define CGC_USB0 (1 << 3)
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#define CGC_SDIO (1 << 4)
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#define CGC_TSU (1 << 5)
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#define CGC_DUNIT (1 << 6)
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#define CGC_RUNIT (1 << 7)
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#define CGC_XOR0 (1 << 8)
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#define CGC_AUDIO (1 << 9)
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#define CGC_SATA0 (1 << 14)
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#define CGC_SATA1 (1 << 15)
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#define CGC_XOR1 (1 << 16)
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#define CGC_CRYPTO (1 << 17)
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#define CGC_PEX1 (1 << 18)
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#define CGC_GE1 (1 << 19)
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#define CGC_TDM (1 << 20)
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#define CGC_RESERVED (0x6 << 21)
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#endif
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