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0ee7261c92
OMAP interconnect drivers are used for the interconnect error handling. Since they are bus driver, lets move it to newly created drivers/bus. Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
339 lines
8.0 KiB
C
339 lines
8.0 KiB
C
/*
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* OMAP3XXX L3 Interconnect Driver header
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*
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* Copyright (C) 2011 Texas Corporation
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* Felipe Balbi <balbi@ti.com>
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* sricharan <r.sricharan@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
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#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
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/* Register definitions. All 64-bit wide */
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#define L3_COMPONENT 0x000
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#define L3_CORE 0x018
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#define L3_AGENT_CONTROL 0x020
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#define L3_AGENT_STATUS 0x028
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#define L3_ERROR_LOG 0x058
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#define L3_ERROR_LOG_MULTI (1 << 31)
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#define L3_ERROR_LOG_SECONDARY (1 << 30)
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#define L3_ERROR_LOG_ADDR 0x060
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/* Register definitions for Sideband Interconnect */
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#define L3_SI_CONTROL 0x020
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#define L3_SI_FLAG_STATUS_0 0x510
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static const u64 shift = 1;
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#define L3_STATUS_0_MPUIA_BRST (shift << 0)
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#define L3_STATUS_0_MPUIA_RSP (shift << 1)
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#define L3_STATUS_0_MPUIA_INBAND (shift << 2)
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#define L3_STATUS_0_IVAIA_BRST (shift << 6)
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#define L3_STATUS_0_IVAIA_RSP (shift << 7)
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#define L3_STATUS_0_IVAIA_INBAND (shift << 8)
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#define L3_STATUS_0_SGXIA_BRST (shift << 9)
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#define L3_STATUS_0_SGXIA_RSP (shift << 10)
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#define L3_STATUS_0_SGXIA_MERROR (shift << 11)
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#define L3_STATUS_0_CAMIA_BRST (shift << 12)
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#define L3_STATUS_0_CAMIA_RSP (shift << 13)
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#define L3_STATUS_0_CAMIA_INBAND (shift << 14)
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#define L3_STATUS_0_DISPIA_BRST (shift << 15)
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#define L3_STATUS_0_DISPIA_RSP (shift << 16)
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#define L3_STATUS_0_DMARDIA_BRST (shift << 18)
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#define L3_STATUS_0_DMARDIA_RSP (shift << 19)
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#define L3_STATUS_0_DMAWRIA_BRST (shift << 21)
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#define L3_STATUS_0_DMAWRIA_RSP (shift << 22)
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#define L3_STATUS_0_USBOTGIA_BRST (shift << 24)
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#define L3_STATUS_0_USBOTGIA_RSP (shift << 25)
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#define L3_STATUS_0_USBOTGIA_INBAND (shift << 26)
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#define L3_STATUS_0_USBHOSTIA_BRST (shift << 27)
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#define L3_STATUS_0_USBHOSTIA_INBAND (shift << 28)
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#define L3_STATUS_0_SMSTA_REQ (shift << 48)
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#define L3_STATUS_0_GPMCTA_REQ (shift << 49)
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#define L3_STATUS_0_OCMRAMTA_REQ (shift << 50)
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#define L3_STATUS_0_OCMROMTA_REQ (shift << 51)
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#define L3_STATUS_0_IVATA_REQ (shift << 54)
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#define L3_STATUS_0_SGXTA_REQ (shift << 55)
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#define L3_STATUS_0_SGXTA_SERROR (shift << 56)
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#define L3_STATUS_0_GPMCTA_SERROR (shift << 57)
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#define L3_STATUS_0_L4CORETA_REQ (shift << 58)
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#define L3_STATUS_0_L4PERTA_REQ (shift << 59)
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#define L3_STATUS_0_L4EMUTA_REQ (shift << 60)
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#define L3_STATUS_0_MAD2DTA_REQ (shift << 61)
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#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \
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| L3_STATUS_0_MPUIA_RSP \
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| L3_STATUS_0_IVAIA_BRST \
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| L3_STATUS_0_IVAIA_RSP \
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| L3_STATUS_0_SGXIA_BRST \
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| L3_STATUS_0_SGXIA_RSP \
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| L3_STATUS_0_CAMIA_BRST \
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| L3_STATUS_0_CAMIA_RSP \
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| L3_STATUS_0_DISPIA_BRST \
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| L3_STATUS_0_DISPIA_RSP \
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| L3_STATUS_0_DMARDIA_BRST \
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| L3_STATUS_0_DMARDIA_RSP \
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| L3_STATUS_0_DMAWRIA_BRST \
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| L3_STATUS_0_DMAWRIA_RSP \
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| L3_STATUS_0_USBOTGIA_BRST \
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| L3_STATUS_0_USBOTGIA_RSP \
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| L3_STATUS_0_USBHOSTIA_BRST \
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| L3_STATUS_0_SMSTA_REQ \
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| L3_STATUS_0_GPMCTA_REQ \
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| L3_STATUS_0_OCMRAMTA_REQ \
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| L3_STATUS_0_OCMROMTA_REQ \
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| L3_STATUS_0_IVATA_REQ \
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| L3_STATUS_0_SGXTA_REQ \
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| L3_STATUS_0_L4CORETA_REQ \
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| L3_STATUS_0_L4PERTA_REQ \
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| L3_STATUS_0_L4EMUTA_REQ \
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| L3_STATUS_0_MAD2DTA_REQ)
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#define L3_SI_FLAG_STATUS_1 0x530
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#define L3_STATUS_1_MPU_DATAIA (1 << 0)
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#define L3_STATUS_1_DAPIA0 (1 << 3)
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#define L3_STATUS_1_DAPIA1 (1 << 4)
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#define L3_STATUS_1_IVAIA (1 << 6)
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#define L3_PM_ERROR_LOG 0x020
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#define L3_PM_CONTROL 0x028
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#define L3_PM_ERROR_CLEAR_SINGLE 0x030
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#define L3_PM_ERROR_CLEAR_MULTI 0x038
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#define L3_PM_REQ_INFO_PERMISSION(n) (0x048 + (0x020 * n))
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#define L3_PM_READ_PERMISSION(n) (0x050 + (0x020 * n))
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#define L3_PM_WRITE_PERMISSION(n) (0x058 + (0x020 * n))
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#define L3_PM_ADDR_MATCH(n) (0x060 + (0x020 * n))
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/* L3 error log bit fields. Common for IA and TA */
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#define L3_ERROR_LOG_CODE 24
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#define L3_ERROR_LOG_INITID 8
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#define L3_ERROR_LOG_CMD 0
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/* L3 agent status bit fields. */
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#define L3_AGENT_STATUS_CLEAR_IA 0x10000000
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#define L3_AGENT_STATUS_CLEAR_TA 0x01000000
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#define OMAP34xx_IRQ_L3_APP 10
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#define L3_APPLICATION_ERROR 0x0
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#define L3_DEBUG_ERROR 0x1
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enum omap3_l3_initiator_id {
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/* LCD has 1 ID */
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OMAP_L3_LCD = 29,
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/* SAD2D has 1 ID */
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OMAP_L3_SAD2D = 28,
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/* MPU has 5 IDs */
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OMAP_L3_IA_MPU_SS_1 = 27,
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OMAP_L3_IA_MPU_SS_2 = 26,
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OMAP_L3_IA_MPU_SS_3 = 25,
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OMAP_L3_IA_MPU_SS_4 = 24,
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OMAP_L3_IA_MPU_SS_5 = 23,
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/* IVA2.2 SS has 3 IDs*/
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OMAP_L3_IA_IVA_SS_1 = 22,
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OMAP_L3_IA_IVA_SS_2 = 21,
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OMAP_L3_IA_IVA_SS_3 = 20,
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/* IVA 2.2 SS DMA has 6 IDS */
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OMAP_L3_IA_IVA_SS_DMA_1 = 19,
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OMAP_L3_IA_IVA_SS_DMA_2 = 18,
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OMAP_L3_IA_IVA_SS_DMA_3 = 17,
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OMAP_L3_IA_IVA_SS_DMA_4 = 16,
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OMAP_L3_IA_IVA_SS_DMA_5 = 15,
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OMAP_L3_IA_IVA_SS_DMA_6 = 14,
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/* SGX has 1 ID */
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OMAP_L3_IA_SGX = 13,
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/* CAM has 3 ID */
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OMAP_L3_IA_CAM_1 = 12,
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OMAP_L3_IA_CAM_2 = 11,
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OMAP_L3_IA_CAM_3 = 10,
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/* DAP has 1 ID */
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OMAP_L3_IA_DAP = 9,
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/* SDMA WR has 2 IDs */
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OMAP_L3_SDMA_WR_1 = 8,
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OMAP_L3_SDMA_WR_2 = 7,
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/* SDMA RD has 4 IDs */
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OMAP_L3_SDMA_RD_1 = 6,
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OMAP_L3_SDMA_RD_2 = 5,
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OMAP_L3_SDMA_RD_3 = 4,
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OMAP_L3_SDMA_RD_4 = 3,
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/* HSUSB OTG has 1 ID */
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OMAP_L3_USBOTG = 2,
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/* HSUSB HOST has 1 ID */
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OMAP_L3_USBHOST = 1,
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};
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enum omap3_l3_code {
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OMAP_L3_CODE_NOERROR = 0,
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OMAP_L3_CODE_UNSUP_CMD = 1,
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OMAP_L3_CODE_ADDR_HOLE = 2,
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OMAP_L3_CODE_PROTECT_VIOLATION = 3,
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OMAP_L3_CODE_IN_BAND_ERR = 4,
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/* codes 5 and 6 are reserved */
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OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
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OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
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/* codes 9 - 15 are also reserved */
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};
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struct omap3_l3 {
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struct device *dev;
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struct clk *ick;
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/* memory base*/
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void __iomem *rt;
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int debug_irq;
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int app_irq;
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/* true when and inband functional error occurs */
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unsigned inband:1;
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};
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/* offsets for l3 agents in order with the Flag status register */
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static unsigned int omap3_l3_app_bases[] = {
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/* MPU IA */
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0x1400,
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0x1400,
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0x1400,
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/* RESERVED */
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0,
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0,
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0,
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/* IVA 2.2 IA */
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0x1800,
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0x1800,
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0x1800,
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/* SGX IA */
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0x1c00,
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0x1c00,
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/* RESERVED */
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0,
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/* CAMERA IA */
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0x5800,
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0x5800,
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0x5800,
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/* DISPLAY IA */
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0x5400,
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0x5400,
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/* RESERVED */
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0,
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/*SDMA RD IA */
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0x4c00,
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0x4c00,
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/* RESERVED */
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0,
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/* SDMA WR IA */
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0x5000,
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0x5000,
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/* RESERVED */
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0,
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/* USB OTG IA */
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0x4400,
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0x4400,
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0x4400,
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/* USB HOST IA */
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0x4000,
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0x4000,
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/* RESERVED */
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0,
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0,
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0,
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0,
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/* SAD2D IA */
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0x3000,
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0x3000,
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0x3000,
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/* RESERVED */
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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/* SMA TA */
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0x2000,
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/* GPMC TA */
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0x2400,
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/* OCM RAM TA */
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0x2800,
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/* OCM ROM TA */
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0x2C00,
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/* L4 CORE TA */
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0x6800,
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/* L4 PER TA */
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0x6c00,
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/* IVA 2.2 TA */
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0x6000,
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/* SGX TA */
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0x6400,
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/* L4 EMU TA */
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0x7000,
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/* GPMC TA */
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0x2400,
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/* L4 CORE TA */
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0x6800,
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/* L4 PER TA */
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0x6c00,
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/* L4 EMU TA */
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0x7000,
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/* MAD2D TA */
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0x3400,
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/* RESERVED */
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0,
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0,
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};
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static unsigned int omap3_l3_debug_bases[] = {
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/* MPU DATA IA */
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0x1400,
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/* RESERVED */
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0,
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0,
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/* DAP IA */
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0x5c00,
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0x5c00,
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/* RESERVED */
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0,
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/* IVA 2.2 IA */
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0x1800,
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/* REST RESERVED */
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};
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static u32 *omap3_l3_bases[] = {
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omap3_l3_app_bases,
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omap3_l3_debug_bases,
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};
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/*
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* REVISIT define __raw_readll/__raw_writell here, but move them to
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* <asm/io.h> at some point
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*/
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#define __raw_writell(v, a) (__chk_io_ptr(a), \
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*(volatile u64 __force *)(a) = (v))
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#define __raw_readll(a) (__chk_io_ptr(a), \
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*(volatile u64 __force *)(a))
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#endif
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