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fb24ea52f7
mmiowb() is now implied by spin_unlock() on architectures that require it, so there is no reason to call it from driver code. This patch was generated using coccinelle: @mmiowb@ @@ - mmiowb(); and invoked as: $ for d in drivers include/linux/qed sound; do \ spatch --include-headers --sp-file mmiowb.cocci --dir $d --in-place; done NOTE: mmiowb() has only ever guaranteed ordering in conjunction with spin_unlock(). However, pairing each mmiowb() removal in this patch with the corresponding call to spin_unlock() is not at all trivial, so there is a small chance that this change may regress any drivers incorrectly relying on mmiowb() to order MMIO writes between CPUs using lock-free synchronisation. If you've ended up bisecting to this commit, you can reintroduce the mmiowb() calls using wmb() instead, which should restore the old behaviour on all architectures other than some esoteric ia64 systems. Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
289 lines
9.4 KiB
C
289 lines
9.4 KiB
C
/****************************************************************************
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* Driver for Solarflare network controllers and boards
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* Copyright 2005-2006 Fen Systems Ltd.
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* Copyright 2006-2013 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#ifndef EF4_IO_H
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#define EF4_IO_H
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#include <linux/io.h>
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#include <linux/spinlock.h>
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/**************************************************************************
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*
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* NIC register I/O
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*
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**************************************************************************
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*
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* Notes on locking strategy for the Falcon architecture:
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*
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* Many CSRs are very wide and cannot be read or written atomically.
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* Writes from the host are buffered by the Bus Interface Unit (BIU)
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* up to 128 bits. Whenever the host writes part of such a register,
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* the BIU collects the written value and does not write to the
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* underlying register until all 4 dwords have been written. A
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* similar buffering scheme applies to host access to the NIC's 64-bit
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* SRAM.
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*
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* Writes to different CSRs and 64-bit SRAM words must be serialised,
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* since interleaved access can result in lost writes. We use
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* ef4_nic::biu_lock for this.
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*
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* We also serialise reads from 128-bit CSRs and SRAM with the same
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* spinlock. This may not be necessary, but it doesn't really matter
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* as there are no such reads on the fast path.
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*
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* The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
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* 128-bit but are special-cased in the BIU to avoid the need for
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* locking in the host:
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*
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* - They are write-only.
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* - The semantics of writing to these registers are such that
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* replacing the low 96 bits with zero does not affect functionality.
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* - If the host writes to the last dword address of such a register
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* (i.e. the high 32 bits) the underlying register will always be
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* written. If the collector and the current write together do not
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* provide values for all 128 bits of the register, the low 96 bits
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* will be written as zero.
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* - If the host writes to the address of any other part of such a
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* register while the collector already holds values for some other
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* register, the write is discarded and the collector maintains its
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* current state.
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*
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* The EF10 architecture exposes very few registers to the host and
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* most of them are only 32 bits wide. The only exceptions are the MC
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* doorbell register pair, which has its own latching, and
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* TX_DESC_UPD, which works in a similar way to the Falcon
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* architecture.
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*/
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#if BITS_PER_LONG == 64
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#define EF4_USE_QWORD_IO 1
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#endif
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#ifdef EF4_USE_QWORD_IO
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static inline void _ef4_writeq(struct ef4_nic *efx, __le64 value,
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unsigned int reg)
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{
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__raw_writeq((__force u64)value, efx->membase + reg);
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}
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static inline __le64 _ef4_readq(struct ef4_nic *efx, unsigned int reg)
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{
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return (__force __le64)__raw_readq(efx->membase + reg);
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}
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#endif
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static inline void _ef4_writed(struct ef4_nic *efx, __le32 value,
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unsigned int reg)
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{
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__raw_writel((__force u32)value, efx->membase + reg);
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}
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static inline __le32 _ef4_readd(struct ef4_nic *efx, unsigned int reg)
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{
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return (__force __le32)__raw_readl(efx->membase + reg);
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}
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/* Write a normal 128-bit CSR, locking as appropriate. */
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static inline void ef4_writeo(struct ef4_nic *efx, const ef4_oword_t *value,
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unsigned int reg)
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{
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unsigned long flags __attribute__ ((unused));
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netif_vdbg(efx, hw, efx->net_dev,
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"writing register %x with " EF4_OWORD_FMT "\n", reg,
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EF4_OWORD_VAL(*value));
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spin_lock_irqsave(&efx->biu_lock, flags);
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#ifdef EF4_USE_QWORD_IO
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_ef4_writeq(efx, value->u64[0], reg + 0);
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_ef4_writeq(efx, value->u64[1], reg + 8);
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#else
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_ef4_writed(efx, value->u32[0], reg + 0);
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_ef4_writed(efx, value->u32[1], reg + 4);
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_ef4_writed(efx, value->u32[2], reg + 8);
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_ef4_writed(efx, value->u32[3], reg + 12);
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#endif
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spin_unlock_irqrestore(&efx->biu_lock, flags);
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}
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/* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
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static inline void ef4_sram_writeq(struct ef4_nic *efx, void __iomem *membase,
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const ef4_qword_t *value, unsigned int index)
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{
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unsigned int addr = index * sizeof(*value);
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unsigned long flags __attribute__ ((unused));
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netif_vdbg(efx, hw, efx->net_dev,
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"writing SRAM address %x with " EF4_QWORD_FMT "\n",
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addr, EF4_QWORD_VAL(*value));
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spin_lock_irqsave(&efx->biu_lock, flags);
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#ifdef EF4_USE_QWORD_IO
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__raw_writeq((__force u64)value->u64[0], membase + addr);
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#else
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__raw_writel((__force u32)value->u32[0], membase + addr);
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__raw_writel((__force u32)value->u32[1], membase + addr + 4);
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#endif
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spin_unlock_irqrestore(&efx->biu_lock, flags);
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}
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/* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
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static inline void ef4_writed(struct ef4_nic *efx, const ef4_dword_t *value,
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unsigned int reg)
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{
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netif_vdbg(efx, hw, efx->net_dev,
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"writing register %x with "EF4_DWORD_FMT"\n",
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reg, EF4_DWORD_VAL(*value));
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/* No lock required */
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_ef4_writed(efx, value->u32[0], reg);
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}
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/* Read a 128-bit CSR, locking as appropriate. */
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static inline void ef4_reado(struct ef4_nic *efx, ef4_oword_t *value,
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unsigned int reg)
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{
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unsigned long flags __attribute__ ((unused));
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spin_lock_irqsave(&efx->biu_lock, flags);
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value->u32[0] = _ef4_readd(efx, reg + 0);
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value->u32[1] = _ef4_readd(efx, reg + 4);
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value->u32[2] = _ef4_readd(efx, reg + 8);
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value->u32[3] = _ef4_readd(efx, reg + 12);
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spin_unlock_irqrestore(&efx->biu_lock, flags);
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netif_vdbg(efx, hw, efx->net_dev,
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"read from register %x, got " EF4_OWORD_FMT "\n", reg,
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EF4_OWORD_VAL(*value));
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}
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/* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
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static inline void ef4_sram_readq(struct ef4_nic *efx, void __iomem *membase,
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ef4_qword_t *value, unsigned int index)
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{
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unsigned int addr = index * sizeof(*value);
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unsigned long flags __attribute__ ((unused));
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spin_lock_irqsave(&efx->biu_lock, flags);
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#ifdef EF4_USE_QWORD_IO
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value->u64[0] = (__force __le64)__raw_readq(membase + addr);
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#else
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value->u32[0] = (__force __le32)__raw_readl(membase + addr);
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value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
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#endif
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spin_unlock_irqrestore(&efx->biu_lock, flags);
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netif_vdbg(efx, hw, efx->net_dev,
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"read from SRAM address %x, got "EF4_QWORD_FMT"\n",
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addr, EF4_QWORD_VAL(*value));
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}
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/* Read a 32-bit CSR or SRAM */
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static inline void ef4_readd(struct ef4_nic *efx, ef4_dword_t *value,
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unsigned int reg)
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{
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value->u32[0] = _ef4_readd(efx, reg);
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netif_vdbg(efx, hw, efx->net_dev,
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"read from register %x, got "EF4_DWORD_FMT"\n",
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reg, EF4_DWORD_VAL(*value));
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}
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/* Write a 128-bit CSR forming part of a table */
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static inline void
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ef4_writeo_table(struct ef4_nic *efx, const ef4_oword_t *value,
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unsigned int reg, unsigned int index)
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{
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ef4_writeo(efx, value, reg + index * sizeof(ef4_oword_t));
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}
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/* Read a 128-bit CSR forming part of a table */
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static inline void ef4_reado_table(struct ef4_nic *efx, ef4_oword_t *value,
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unsigned int reg, unsigned int index)
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{
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ef4_reado(efx, value, reg + index * sizeof(ef4_oword_t));
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}
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/* Page size used as step between per-VI registers */
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#define EF4_VI_PAGE_SIZE 0x2000
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/* Calculate offset to page-mapped register */
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#define EF4_PAGED_REG(page, reg) \
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((page) * EF4_VI_PAGE_SIZE + (reg))
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/* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
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static inline void _ef4_writeo_page(struct ef4_nic *efx, ef4_oword_t *value,
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unsigned int reg, unsigned int page)
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{
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reg = EF4_PAGED_REG(page, reg);
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netif_vdbg(efx, hw, efx->net_dev,
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"writing register %x with " EF4_OWORD_FMT "\n", reg,
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EF4_OWORD_VAL(*value));
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#ifdef EF4_USE_QWORD_IO
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_ef4_writeq(efx, value->u64[0], reg + 0);
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_ef4_writeq(efx, value->u64[1], reg + 8);
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#else
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_ef4_writed(efx, value->u32[0], reg + 0);
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_ef4_writed(efx, value->u32[1], reg + 4);
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_ef4_writed(efx, value->u32[2], reg + 8);
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_ef4_writed(efx, value->u32[3], reg + 12);
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#endif
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}
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#define ef4_writeo_page(efx, value, reg, page) \
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_ef4_writeo_page(efx, value, \
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reg + \
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BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
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page)
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/* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the
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* high bits of RX_DESC_UPD or TX_DESC_UPD)
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*/
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static inline void
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_ef4_writed_page(struct ef4_nic *efx, const ef4_dword_t *value,
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unsigned int reg, unsigned int page)
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{
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ef4_writed(efx, value, EF4_PAGED_REG(page, reg));
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}
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#define ef4_writed_page(efx, value, reg, page) \
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_ef4_writed_page(efx, value, \
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reg + \
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BUILD_BUG_ON_ZERO((reg) != 0x400 && \
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(reg) != 0x420 && \
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(reg) != 0x830 && \
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(reg) != 0x83c && \
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(reg) != 0xa18 && \
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(reg) != 0xa1c), \
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page)
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/* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug
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* in the BIU means that writes to TIMER_COMMAND[0] invalidate the
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* collector register.
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*/
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static inline void _ef4_writed_page_locked(struct ef4_nic *efx,
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const ef4_dword_t *value,
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unsigned int reg,
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unsigned int page)
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{
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unsigned long flags __attribute__ ((unused));
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if (page == 0) {
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spin_lock_irqsave(&efx->biu_lock, flags);
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ef4_writed(efx, value, EF4_PAGED_REG(page, reg));
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spin_unlock_irqrestore(&efx->biu_lock, flags);
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} else {
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ef4_writed(efx, value, EF4_PAGED_REG(page, reg));
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}
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}
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#define ef4_writed_page_locked(efx, value, reg, page) \
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_ef4_writed_page_locked(efx, value, \
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reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
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page)
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#endif /* EF4_IO_H */
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