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da3e02a236
This patch adds a reset controller node to the SOC device tree and also adds new header files with reset lines required for other device tree nodes. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
156 lines
3.8 KiB
Plaintext
156 lines
3.8 KiB
Plaintext
/*
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* Copyright (C) 2012 STMicroelectronics Limited.
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* Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*/
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#include "stih41x.dtsi"
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#include "stih416-clock.dtsi"
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#include "stih416-pinctrl.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset-controller/stih416-resets.h>
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/ {
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L2: cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0xfffe2000 0x1000>;
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arm,data-latency = <3 3 3>;
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arm,tag-latency = <2 2 2>;
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cache-unified;
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cache-level = <2>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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compatible = "simple-bus";
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powerdown: powerdown-controller {
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#reset-cells = <1>;
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compatible = "st,stih416-powerdown";
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};
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syscfg_sbc:sbc-syscfg@fe600000{
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compatible = "st,stih416-sbc-syscfg", "syscon";
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reg = <0xfe600000 0x1000>;
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};
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syscfg_front:front-syscfg@fee10000{
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compatible = "st,stih416-front-syscfg", "syscon";
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reg = <0xfee10000 0x1000>;
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};
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syscfg_rear:rear-syscfg@fe830000{
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compatible = "st,stih416-rear-syscfg", "syscon";
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reg = <0xfe830000 0x1000>;
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};
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/* MPE */
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syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{
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compatible = "st,stih416-fvdp-fe-syscfg", "syscon";
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reg = <0xfddf0000 0x1000>;
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};
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syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{
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compatible = "st,stih416-fvdp-lite-syscfg", "syscon";
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reg = <0xfd6a0000 0x1000>;
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};
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syscfg_cpu:cpu-syscfg@fdde0000{
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compatible = "st,stih416-cpu-syscfg", "syscon";
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reg = <0xfdde0000 0x1000>;
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};
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syscfg_compo:compo-syscfg@fd320000{
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compatible = "st,stih416-compo-syscfg", "syscon";
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reg = <0xfd320000 0x1000>;
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};
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syscfg_transport:transport-syscfg@fd690000{
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compatible = "st,stih416-transport-syscfg", "syscon";
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reg = <0xfd690000 0x1000>;
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};
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syscfg_lpm:lpm-syscfg@fe4b5100{
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compatible = "st,stih416-lpm-syscfg", "syscon";
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reg = <0xfe4b5100 0x8>;
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};
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serial2: serial@fed32000{
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compatible = "st,asc";
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status = "disabled";
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reg = <0xfed32000 0x2c>;
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interrupts = <0 197 0>;
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clocks = <&CLK_S_ICN_REG_0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>;
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};
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/* SBC_UART1 */
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sbc_serial1: serial@fe531000 {
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compatible = "st,asc";
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status = "disabled";
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reg = <0xfe531000 0x2c>;
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interrupts = <0 210 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sbc_serial1>;
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clocks = <&CLK_SYSIN>;
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};
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i2c@fed40000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0xfed40000 0x110>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&CLK_S_ICN_REG_0>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0_default>;
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status = "disabled";
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};
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i2c@fed41000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0xfed41000 0x110>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&CLK_S_ICN_REG_0>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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status = "disabled";
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};
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i2c@fe540000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0xfe540000 0x110>;
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interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&CLK_SYSIN>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sbc_i2c0_default>;
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status = "disabled";
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};
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i2c@fe541000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0xfe541000 0x110>;
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interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&CLK_SYSIN>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sbc_i2c1_default>;
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status = "disabled";
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};
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};
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};
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