mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 20:53:53 +08:00
1ababe1148
Create the firmware_has_feature() inline and move the firmware feature stuff into its own header file. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
572 lines
15 KiB
C
572 lines
15 KiB
C
/*
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* arch/ppc64/kernel/pSeries_iommu.c
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*
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* Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
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*
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* Rewrite, cleanup:
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*
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* Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
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*
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* Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/rtas.h>
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#include <asm/ppcdebug.h>
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#include <asm/iommu.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/abs_addr.h>
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#include <asm/plpar_wrappers.h>
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#include <asm/pSeries_reconfig.h>
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#include <asm/systemcfg.h>
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#include <asm/firmware.h>
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#include "pci.h"
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#define DBG(fmt...)
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extern int is_python(struct device_node *);
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static void tce_build_pSeries(struct iommu_table *tbl, long index,
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long npages, unsigned long uaddr,
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enum dma_data_direction direction)
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{
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union tce_entry t;
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union tce_entry *tp;
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t.te_word = 0;
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t.te_rdwr = 1; // Read allowed
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if (direction != DMA_TO_DEVICE)
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t.te_pciwr = 1;
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tp = ((union tce_entry *)tbl->it_base) + index;
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while (npages--) {
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/* can't move this out since we might cross LMB boundary */
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t.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT;
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tp->te_word = t.te_word;
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uaddr += PAGE_SIZE;
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tp++;
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}
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}
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static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
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{
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union tce_entry t;
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union tce_entry *tp;
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t.te_word = 0;
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tp = ((union tce_entry *)tbl->it_base) + index;
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while (npages--) {
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tp->te_word = t.te_word;
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tp++;
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}
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}
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static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
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long npages, unsigned long uaddr,
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enum dma_data_direction direction)
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{
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u64 rc;
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union tce_entry tce;
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tce.te_word = 0;
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tce.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT;
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tce.te_rdwr = 1;
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if (direction != DMA_TO_DEVICE)
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tce.te_pciwr = 1;
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while (npages--) {
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rc = plpar_tce_put((u64)tbl->it_index,
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(u64)tcenum << 12,
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tce.te_word );
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if (rc && printk_ratelimit()) {
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printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
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printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
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printk("\ttcenum = 0x%lx\n", (u64)tcenum);
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printk("\ttce val = 0x%lx\n", tce.te_word );
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show_stack(current, (unsigned long *)__get_SP());
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}
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tcenum++;
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tce.te_rpn++;
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}
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}
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static DEFINE_PER_CPU(void *, tce_page) = NULL;
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static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
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long npages, unsigned long uaddr,
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enum dma_data_direction direction)
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{
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u64 rc;
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union tce_entry tce, *tcep;
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long l, limit;
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if (npages == 1)
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return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
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direction);
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tcep = __get_cpu_var(tce_page);
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/* This is safe to do since interrupts are off when we're called
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* from iommu_alloc{,_sg}()
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*/
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if (!tcep) {
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tcep = (void *)__get_free_page(GFP_ATOMIC);
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/* If allocation fails, fall back to the loop implementation */
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if (!tcep)
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return tce_build_pSeriesLP(tbl, tcenum, npages,
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uaddr, direction);
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__get_cpu_var(tce_page) = tcep;
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}
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tce.te_word = 0;
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tce.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT;
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tce.te_rdwr = 1;
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if (direction != DMA_TO_DEVICE)
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tce.te_pciwr = 1;
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/* We can map max one pageful of TCEs at a time */
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do {
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/*
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* Set up the page with TCE data, looping through and setting
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* the values.
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*/
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limit = min_t(long, npages, PAGE_SIZE/sizeof(union tce_entry));
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for (l = 0; l < limit; l++) {
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tcep[l] = tce;
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tce.te_rpn++;
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}
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rc = plpar_tce_put_indirect((u64)tbl->it_index,
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(u64)tcenum << 12,
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(u64)virt_to_abs(tcep),
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limit);
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npages -= limit;
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tcenum += limit;
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} while (npages > 0 && !rc);
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if (rc && printk_ratelimit()) {
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printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
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printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
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printk("\tnpages = 0x%lx\n", (u64)npages);
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printk("\ttce[0] val = 0x%lx\n", tcep[0].te_word);
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show_stack(current, (unsigned long *)__get_SP());
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}
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}
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static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
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{
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u64 rc;
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union tce_entry tce;
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tce.te_word = 0;
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while (npages--) {
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rc = plpar_tce_put((u64)tbl->it_index,
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(u64)tcenum << 12,
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tce.te_word);
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if (rc && printk_ratelimit()) {
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printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
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printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
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printk("\ttcenum = 0x%lx\n", (u64)tcenum);
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printk("\ttce val = 0x%lx\n", tce.te_word );
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show_stack(current, (unsigned long *)__get_SP());
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}
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tcenum++;
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}
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}
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static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
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{
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u64 rc;
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union tce_entry tce;
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tce.te_word = 0;
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rc = plpar_tce_stuff((u64)tbl->it_index,
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(u64)tcenum << 12,
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tce.te_word,
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npages);
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if (rc && printk_ratelimit()) {
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printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
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printk("\trc = %ld\n", rc);
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printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
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printk("\tnpages = 0x%lx\n", (u64)npages);
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printk("\ttce val = 0x%lx\n", tce.te_word );
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show_stack(current, (unsigned long *)__get_SP());
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}
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}
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static void iommu_table_setparms(struct pci_controller *phb,
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struct device_node *dn,
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struct iommu_table *tbl)
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{
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struct device_node *node;
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unsigned long *basep;
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unsigned int *sizep;
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node = (struct device_node *)phb->arch_data;
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basep = (unsigned long *)get_property(node, "linux,tce-base", NULL);
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sizep = (unsigned int *)get_property(node, "linux,tce-size", NULL);
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if (basep == NULL || sizep == NULL) {
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printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
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"missing tce entries !\n", dn->full_name);
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return;
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}
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tbl->it_base = (unsigned long)__va(*basep);
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memset((void *)tbl->it_base, 0, *sizep);
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tbl->it_busno = phb->bus->number;
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/* Units of tce entries */
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tbl->it_offset = phb->dma_window_base_cur >> PAGE_SHIFT;
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/* Test if we are going over 2GB of DMA space */
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if (phb->dma_window_base_cur + phb->dma_window_size > (1L << 31))
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panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
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phb->dma_window_base_cur += phb->dma_window_size;
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/* Set the tce table size - measured in entries */
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tbl->it_size = phb->dma_window_size >> PAGE_SHIFT;
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tbl->it_index = 0;
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tbl->it_blocksize = 16;
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tbl->it_type = TCE_PCI;
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}
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/*
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* iommu_table_setparms_lpar
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*
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* Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
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*
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* ToDo: properly interpret the ibm,dma-window property. The definition is:
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* logical-bus-number (1 word)
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* phys-address (#address-cells words)
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* size (#cell-size words)
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*
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* Currently we hard code these sizes (more or less).
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*/
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static void iommu_table_setparms_lpar(struct pci_controller *phb,
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struct device_node *dn,
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struct iommu_table *tbl,
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unsigned int *dma_window)
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{
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tbl->it_busno = dn->bussubno;
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/* TODO: Parse field size properties properly. */
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tbl->it_size = (((unsigned long)dma_window[4] << 32) |
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(unsigned long)dma_window[5]) >> PAGE_SHIFT;
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tbl->it_offset = (((unsigned long)dma_window[2] << 32) |
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(unsigned long)dma_window[3]) >> PAGE_SHIFT;
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tbl->it_base = 0;
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tbl->it_index = dma_window[0];
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tbl->it_blocksize = 16;
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tbl->it_type = TCE_PCI;
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}
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static void iommu_bus_setup_pSeries(struct pci_bus *bus)
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{
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struct device_node *dn, *pdn;
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struct iommu_table *tbl;
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DBG("iommu_bus_setup_pSeries, bus %p, bus->self %p\n", bus, bus->self);
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/* For each (root) bus, we carve up the available DMA space in 256MB
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* pieces. Since each piece is used by one (sub) bus/device, that would
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* give a maximum of 7 devices per PHB. In most cases, this is plenty.
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*
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* The exception is on Python PHBs (pre-POWER4). Here we don't have EADS
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* bridges below the PHB to allocate the sectioned tables to, so instead
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* we allocate a 1GB table at the PHB level.
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*/
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dn = pci_bus_to_OF_node(bus);
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if (!bus->self) {
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/* Root bus */
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if (is_python(dn)) {
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unsigned int *iohole;
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DBG("Python root bus %s\n", bus->name);
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iohole = (unsigned int *)get_property(dn, "io-hole", 0);
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if (iohole) {
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/* On first bus we need to leave room for the
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* ISA address space. Just skip the first 256MB
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* alltogether. This leaves 768MB for the window.
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*/
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DBG("PHB has io-hole, reserving 256MB\n");
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dn->phb->dma_window_size = 3 << 28;
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dn->phb->dma_window_base_cur = 1 << 28;
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} else {
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/* 1GB window by default */
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dn->phb->dma_window_size = 1 << 30;
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dn->phb->dma_window_base_cur = 0;
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}
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tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL);
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iommu_table_setparms(dn->phb, dn, tbl);
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dn->iommu_table = iommu_init_table(tbl);
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} else {
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/* Do a 128MB table at root. This is used for the IDE
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* controller on some SMP-mode POWER4 machines. It
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* doesn't hurt to allocate it on other machines
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* -- it'll just be unused since new tables are
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* allocated on the EADS level.
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*
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* Allocate at offset 128MB to avoid having to deal
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* with ISA holes; 128MB table for IDE is plenty.
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*/
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dn->phb->dma_window_size = 1 << 27;
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dn->phb->dma_window_base_cur = 1 << 27;
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tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL);
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iommu_table_setparms(dn->phb, dn, tbl);
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dn->iommu_table = iommu_init_table(tbl);
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/* All child buses have 256MB tables */
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dn->phb->dma_window_size = 1 << 28;
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}
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} else {
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pdn = pci_bus_to_OF_node(bus->parent);
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if (!bus->parent->self && !is_python(pdn)) {
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struct iommu_table *tbl;
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/* First child and not python means this is the EADS
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* level. Allocate new table for this slot with 256MB
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* window.
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*/
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tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL);
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iommu_table_setparms(dn->phb, dn, tbl);
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dn->iommu_table = iommu_init_table(tbl);
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} else {
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/* Lower than first child or under python, use parent table */
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dn->iommu_table = pdn->iommu_table;
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}
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}
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}
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static void iommu_bus_setup_pSeriesLP(struct pci_bus *bus)
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{
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struct iommu_table *tbl;
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struct device_node *dn, *pdn;
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unsigned int *dma_window = NULL;
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DBG("iommu_bus_setup_pSeriesLP, bus %p, bus->self %p\n", bus, bus->self);
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dn = pci_bus_to_OF_node(bus);
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/* Find nearest ibm,dma-window, walking up the device tree */
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for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
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dma_window = (unsigned int *)get_property(pdn, "ibm,dma-window", NULL);
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if (dma_window != NULL)
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break;
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}
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if (dma_window == NULL) {
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DBG("iommu_bus_setup_pSeriesLP: bus %s seems to have no ibm,dma-window property\n", dn->full_name);
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return;
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}
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if (!pdn->iommu_table) {
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/* Bussubno hasn't been copied yet.
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* Do it now because iommu_table_setparms_lpar needs it.
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*/
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pdn->bussubno = bus->number;
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tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table),
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GFP_KERNEL);
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iommu_table_setparms_lpar(pdn->phb, pdn, tbl, dma_window);
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pdn->iommu_table = iommu_init_table(tbl);
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}
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if (pdn != dn)
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dn->iommu_table = pdn->iommu_table;
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}
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static void iommu_dev_setup_pSeries(struct pci_dev *dev)
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{
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struct device_node *dn, *mydn;
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DBG("iommu_dev_setup_pSeries, dev %p (%s)\n", dev, dev->pretty_name);
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/* Now copy the iommu_table ptr from the bus device down to the
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* pci device_node. This means get_iommu_table() won't need to search
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* up the device tree to find it.
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*/
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mydn = dn = pci_device_to_OF_node(dev);
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while (dn && dn->iommu_table == NULL)
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dn = dn->parent;
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if (dn) {
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mydn->iommu_table = dn->iommu_table;
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} else {
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DBG("iommu_dev_setup_pSeries, dev %p (%s) has no iommu table\n", dev, dev->pretty_name);
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}
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}
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static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
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{
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int err = NOTIFY_OK;
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struct device_node *np = node;
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switch (action) {
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case PSERIES_RECONFIG_REMOVE:
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if (np->iommu_table &&
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get_property(np, "ibm,dma-window", NULL))
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iommu_free_table(np);
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break;
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default:
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err = NOTIFY_DONE;
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break;
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}
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return err;
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}
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static struct notifier_block iommu_reconfig_nb = {
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.notifier_call = iommu_reconfig_notifier,
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};
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static void iommu_dev_setup_pSeriesLP(struct pci_dev *dev)
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{
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struct device_node *pdn, *dn;
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struct iommu_table *tbl;
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int *dma_window = NULL;
|
|
|
|
DBG("iommu_dev_setup_pSeriesLP, dev %p (%s)\n", dev, dev->pretty_name);
|
|
|
|
/* dev setup for LPAR is a little tricky, since the device tree might
|
|
* contain the dma-window properties per-device and not neccesarily
|
|
* for the bus. So we need to search upwards in the tree until we
|
|
* either hit a dma-window property, OR find a parent with a table
|
|
* already allocated.
|
|
*/
|
|
dn = pci_device_to_OF_node(dev);
|
|
|
|
for (pdn = dn; pdn && !pdn->iommu_table; pdn = pdn->parent) {
|
|
dma_window = (unsigned int *)get_property(pdn, "ibm,dma-window", NULL);
|
|
if (dma_window)
|
|
break;
|
|
}
|
|
|
|
/* Check for parent == NULL so we don't try to setup the empty EADS
|
|
* slots on POWER4 machines.
|
|
*/
|
|
if (dma_window == NULL || pdn->parent == NULL) {
|
|
/* Fall back to regular (non-LPAR) dev setup */
|
|
DBG("No dma window for device, falling back to regular setup\n");
|
|
iommu_dev_setup_pSeries(dev);
|
|
return;
|
|
} else {
|
|
DBG("Found DMA window, allocating table\n");
|
|
}
|
|
|
|
if (!pdn->iommu_table) {
|
|
/* iommu_table_setparms_lpar needs bussubno. */
|
|
pdn->bussubno = pdn->phb->bus->number;
|
|
|
|
tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table),
|
|
GFP_KERNEL);
|
|
|
|
iommu_table_setparms_lpar(pdn->phb, pdn, tbl, dma_window);
|
|
|
|
pdn->iommu_table = iommu_init_table(tbl);
|
|
}
|
|
|
|
if (pdn != dn)
|
|
dn->iommu_table = pdn->iommu_table;
|
|
}
|
|
|
|
static void iommu_bus_setup_null(struct pci_bus *b) { }
|
|
static void iommu_dev_setup_null(struct pci_dev *d) { }
|
|
|
|
/* These are called very early. */
|
|
void iommu_init_early_pSeries(void)
|
|
{
|
|
if (of_chosen && get_property(of_chosen, "linux,iommu-off", NULL)) {
|
|
/* Direct I/O, IOMMU off */
|
|
ppc_md.iommu_dev_setup = iommu_dev_setup_null;
|
|
ppc_md.iommu_bus_setup = iommu_bus_setup_null;
|
|
pci_direct_iommu_init();
|
|
|
|
return;
|
|
}
|
|
|
|
if (systemcfg->platform & PLATFORM_LPAR) {
|
|
if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
|
|
ppc_md.tce_build = tce_buildmulti_pSeriesLP;
|
|
ppc_md.tce_free = tce_freemulti_pSeriesLP;
|
|
} else {
|
|
ppc_md.tce_build = tce_build_pSeriesLP;
|
|
ppc_md.tce_free = tce_free_pSeriesLP;
|
|
}
|
|
ppc_md.iommu_bus_setup = iommu_bus_setup_pSeriesLP;
|
|
ppc_md.iommu_dev_setup = iommu_dev_setup_pSeriesLP;
|
|
} else {
|
|
ppc_md.tce_build = tce_build_pSeries;
|
|
ppc_md.tce_free = tce_free_pSeries;
|
|
ppc_md.iommu_bus_setup = iommu_bus_setup_pSeries;
|
|
ppc_md.iommu_dev_setup = iommu_dev_setup_pSeries;
|
|
}
|
|
|
|
|
|
pSeries_reconfig_notifier_register(&iommu_reconfig_nb);
|
|
|
|
pci_iommu_init();
|
|
}
|
|
|