mirror of
https://github.com/edk2-porting/linux-next.git
synced 2025-01-09 06:04:05 +08:00
d9295746c0
Mark the SRAM (aka OCM RAM) as Non-cacheable Normal memory[1]. This is to prevent the ARM from evicting existing cache lines to SDRAM while code is executing from the SRAM. Necessary since one of the primary uses for the SRAM is to hold the code and data for the CORE DPLL M2 divider reprogramming code, which must execute while the SDRC is idled. If the ARM attempts to write cache lines back to the while the SRAM code is running, the ARM will stall[2]. TI deals with this problem in the CDP kernel by marking the SRAM as Strongly-ordered memory. Tero Kristo <tero.kristo@nokia.com> caught a bug in an earlier version of this patch - thanks Tero. ... 1. ARMv7 ARM (DDI 0406A) pp. A3-30, A3-31, B3-32. 2. Private communication with Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <tero.kristo@nokia.com> Cc: Richard Woodruff <r-woodruff2@ti.com> |
||
|---|---|---|
| .. | ||
| include/mach | ||
| clock.c | ||
| common.c | ||
| cpu-omap.c | ||
| debug-devices.c | ||
| debug-leds.c | ||
| devices.c | ||
| dma.c | ||
| dmtimer.c | ||
| fb.c | ||
| gpio.c | ||
| i2c.c | ||
| io.c | ||
| Kconfig | ||
| mailbox.c | ||
| Makefile | ||
| mcbsp.c | ||
| mux.c | ||
| ocpi.c | ||
| sram.c | ||
| usb.c | ||