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d8f64797c5
Many of the Tegra DT binding documents say nothing about the clocks or clock-names properties, yet those are present and required in DT files. This patch simply updates the documentation file to match the implicit definition of the binding, based on real-world DT content. All Tegra bindings that mention clocks are updated to have consistent wording and formatting of the clock-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
251 lines
7.6 KiB
Plaintext
251 lines
7.6 KiB
Plaintext
NVIDIA Tegra host1x
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Required properties:
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- compatible: "nvidia,tegra<chip>-host1x"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- #address-cells: The number of cells used to represent physical base addresses
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in the host1x address space. Should be 1.
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- #size-cells: The number of cells used to represent the size of an address
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range in the host1x address space. Should be 1.
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- ranges: The mapping of the host1x address space to the CPU address space.
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- clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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The host1x top-level node defines a number of children, each representing one
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of the following host1x client modules:
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- mpe: video encoder
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Required properties:
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- compatible: "nvidia,tegra<chip>-mpe"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- vi: video input
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Required properties:
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- compatible: "nvidia,tegra<chip>-vi"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- epp: encoder pre-processor
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Required properties:
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- compatible: "nvidia,tegra<chip>-epp"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- isp: image signal processor
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Required properties:
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- compatible: "nvidia,tegra<chip>-isp"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- gr2d: 2D graphics engine
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Required properties:
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- compatible: "nvidia,tegra<chip>-gr2d"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- gr3d: 3D graphics engine
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Required properties:
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- compatible: "nvidia,tegra<chip>-gr3d"
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- reg: Physical base address and length of the controller's registers.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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(This property may be omitted if the only clock in the list is "3d")
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- 3d
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This MUST be the first entry.
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- 3d2 (Only required on SoCs with two 3D clocks)
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- dc: display controller
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Required properties:
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- compatible: "nvidia,tegra<chip>-dc"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- dc
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This MUST be the first entry.
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- parent
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Each display controller node has a child node, named "rgb", that represents
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the RGB output associated with the controller. It can take the following
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optional properties:
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- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
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- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
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- nvidia,edid: supplies a binary EDID blob
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- hdmi: High Definition Multimedia Interface
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Required properties:
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- compatible: "nvidia,tegra<chip>-hdmi"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- vdd-supply: regulator for supply voltage
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- pll-supply: regulator for PLL
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- hdmi
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This MUST be the first entry.
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- parent
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Optional properties:
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- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
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- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
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- nvidia,edid: supplies a binary EDID blob
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- tvo: TV encoder output
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Required properties:
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- compatible: "nvidia,tegra<chip>-tvo"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- dsi: display serial interface
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Required properties:
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- compatible: "nvidia,tegra<chip>-dsi"
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- reg: Physical base address and length of the controller's registers.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- dsi
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This MUST be the first entry.
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- parent
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Example:
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/ {
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...
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host1x {
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compatible = "nvidia,tegra20-host1x", "simple-bus";
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reg = <0x50000000 0x00024000>;
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interrupts = <0 65 0x04 /* mpcore syncpt */
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0 67 0x04>; /* mpcore general */
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clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x54000000 0x54000000 0x04000000>;
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mpe {
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compatible = "nvidia,tegra20-mpe";
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reg = <0x54040000 0x00040000>;
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interrupts = <0 68 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_MPE>;
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};
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vi {
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compatible = "nvidia,tegra20-vi";
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reg = <0x54080000 0x00040000>;
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interrupts = <0 69 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_VI>;
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};
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epp {
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compatible = "nvidia,tegra20-epp";
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reg = <0x540c0000 0x00040000>;
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interrupts = <0 70 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_EPP>;
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};
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isp {
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compatible = "nvidia,tegra20-isp";
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reg = <0x54100000 0x00040000>;
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interrupts = <0 71 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_ISP>;
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};
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gr2d {
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compatible = "nvidia,tegra20-gr2d";
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reg = <0x54140000 0x00040000>;
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interrupts = <0 72 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_GR2D>;
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};
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gr3d {
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compatible = "nvidia,tegra20-gr3d";
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reg = <0x54180000 0x00040000>;
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clocks = <&tegra_car TEGRA20_CLK_GR3D>;
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};
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dc@54200000 {
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compatible = "nvidia,tegra20-dc";
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reg = <0x54200000 0x00040000>;
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interrupts = <0 73 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_DISP1>,
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<&tegra_car TEGRA20_CLK_PLL_P>;
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clock-names = "disp1", "parent";
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rgb {
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status = "disabled";
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};
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};
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dc@54240000 {
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compatible = "nvidia,tegra20-dc";
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reg = <0x54240000 0x00040000>;
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interrupts = <0 74 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_DISP2>,
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<&tegra_car TEGRA20_CLK_PLL_P>;
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clock-names = "disp2", "parent";
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rgb {
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status = "disabled";
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};
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};
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hdmi {
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compatible = "nvidia,tegra20-hdmi";
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reg = <0x54280000 0x00040000>;
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interrupts = <0 75 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_HDMI>,
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<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
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clock-names = "hdmi", "parent";
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status = "disabled";
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};
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tvo {
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compatible = "nvidia,tegra20-tvo";
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reg = <0x542c0000 0x00040000>;
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interrupts = <0 76 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_TVO>;
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status = "disabled";
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};
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dsi {
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compatible = "nvidia,tegra20-dsi";
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reg = <0x54300000 0x00040000>;
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clocks = <&tegra_car TEGRA20_CLK_DSI>,
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<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
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clock-names = "dsi", "parent";
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status = "disabled";
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};
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};
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...
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};
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