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1965aae3c9
Change header guards named "ASM_X86__*" to "_ASM_X86_*" since: a. the double underscore is ugly and pointless. b. no leading underscore violates namespace constraints. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
362 lines
7.9 KiB
C
362 lines
7.9 KiB
C
#ifndef _ASM_X86_XOR_64_H
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#define _ASM_X86_XOR_64_H
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/*
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* Optimized RAID-5 checksumming functions for MMX and SSE.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* You should have received a copy of the GNU General Public License
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* (for example /usr/src/linux/COPYING); if not, write to the Free
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* Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/*
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* Cache avoiding checksumming functions utilizing KNI instructions
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* Copyright (C) 1999 Zach Brown (with obvious credit due Ingo)
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*/
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/*
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* Based on
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* High-speed RAID5 checksumming functions utilizing SSE instructions.
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* Copyright (C) 1998 Ingo Molnar.
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*/
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/*
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* x86-64 changes / gcc fixes from Andi Kleen.
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* Copyright 2002 Andi Kleen, SuSE Labs.
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*
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* This hasn't been optimized for the hammer yet, but there are likely
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* no advantages to be gotten from x86-64 here anyways.
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*/
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typedef struct {
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unsigned long a, b;
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} __attribute__((aligned(16))) xmm_store_t;
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/* Doesn't use gcc to save the XMM registers, because there is no easy way to
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tell it to do a clts before the register saving. */
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#define XMMS_SAVE \
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do { \
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preempt_disable(); \
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asm volatile( \
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"movq %%cr0,%0 ;\n\t" \
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"clts ;\n\t" \
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"movups %%xmm0,(%1) ;\n\t" \
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"movups %%xmm1,0x10(%1) ;\n\t" \
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"movups %%xmm2,0x20(%1) ;\n\t" \
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"movups %%xmm3,0x30(%1) ;\n\t" \
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: "=&r" (cr0) \
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: "r" (xmm_save) \
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: "memory"); \
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} while (0)
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#define XMMS_RESTORE \
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do { \
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asm volatile( \
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"sfence ;\n\t" \
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"movups (%1),%%xmm0 ;\n\t" \
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"movups 0x10(%1),%%xmm1 ;\n\t" \
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"movups 0x20(%1),%%xmm2 ;\n\t" \
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"movups 0x30(%1),%%xmm3 ;\n\t" \
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"movq %0,%%cr0 ;\n\t" \
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: \
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: "r" (cr0), "r" (xmm_save) \
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: "memory"); \
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preempt_enable(); \
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} while (0)
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#define OFFS(x) "16*("#x")"
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#define PF_OFFS(x) "256+16*("#x")"
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#define PF0(x) " prefetchnta "PF_OFFS(x)"(%[p1]) ;\n"
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#define LD(x, y) " movaps "OFFS(x)"(%[p1]), %%xmm"#y" ;\n"
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#define ST(x, y) " movaps %%xmm"#y", "OFFS(x)"(%[p1]) ;\n"
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#define PF1(x) " prefetchnta "PF_OFFS(x)"(%[p2]) ;\n"
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#define PF2(x) " prefetchnta "PF_OFFS(x)"(%[p3]) ;\n"
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#define PF3(x) " prefetchnta "PF_OFFS(x)"(%[p4]) ;\n"
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#define PF4(x) " prefetchnta "PF_OFFS(x)"(%[p5]) ;\n"
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#define PF5(x) " prefetchnta "PF_OFFS(x)"(%[p6]) ;\n"
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#define XO1(x, y) " xorps "OFFS(x)"(%[p2]), %%xmm"#y" ;\n"
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#define XO2(x, y) " xorps "OFFS(x)"(%[p3]), %%xmm"#y" ;\n"
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#define XO3(x, y) " xorps "OFFS(x)"(%[p4]), %%xmm"#y" ;\n"
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#define XO4(x, y) " xorps "OFFS(x)"(%[p5]), %%xmm"#y" ;\n"
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#define XO5(x, y) " xorps "OFFS(x)"(%[p6]), %%xmm"#y" ;\n"
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static void
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xor_sse_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
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{
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unsigned int lines = bytes >> 8;
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unsigned long cr0;
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xmm_store_t xmm_save[4];
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XMMS_SAVE;
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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LD(i, 0) \
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LD(i + 1, 1) \
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PF1(i) \
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PF1(i + 2) \
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LD(i + 2, 2) \
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LD(i + 3, 3) \
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PF0(i + 4) \
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PF0(i + 6) \
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XO1(i, 0) \
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XO1(i + 1, 1) \
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XO1(i + 2, 2) \
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XO1(i + 3, 3) \
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ST(i, 0) \
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ST(i + 1, 1) \
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ST(i + 2, 2) \
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ST(i + 3, 3) \
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PF0(0)
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PF0(2)
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" addq %[inc], %[p1] ;\n"
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" addq %[inc], %[p2] ;\n"
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" decl %[cnt] ; jnz 1b"
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: [p1] "+r" (p1), [p2] "+r" (p2), [cnt] "+r" (lines)
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: [inc] "r" (256UL)
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: "memory");
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XMMS_RESTORE;
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}
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static void
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xor_sse_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3)
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{
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unsigned int lines = bytes >> 8;
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xmm_store_t xmm_save[4];
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unsigned long cr0;
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XMMS_SAVE;
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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PF1(i) \
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PF1(i + 2) \
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LD(i, 0) \
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LD(i + 1, 1) \
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LD(i + 2, 2) \
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LD(i + 3, 3) \
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PF2(i) \
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PF2(i + 2) \
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PF0(i + 4) \
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PF0(i + 6) \
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XO1(i, 0) \
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XO1(i + 1, 1) \
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XO1(i + 2, 2) \
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XO1(i + 3, 3) \
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XO2(i, 0) \
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XO2(i + 1, 1) \
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XO2(i + 2, 2) \
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XO2(i + 3, 3) \
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ST(i, 0) \
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ST(i + 1, 1) \
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ST(i + 2, 2) \
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ST(i + 3, 3) \
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PF0(0)
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PF0(2)
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" addq %[inc], %[p1] ;\n"
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" addq %[inc], %[p2] ;\n"
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" addq %[inc], %[p3] ;\n"
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" decl %[cnt] ; jnz 1b"
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: [cnt] "+r" (lines),
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[p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3)
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: [inc] "r" (256UL)
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: "memory");
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XMMS_RESTORE;
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}
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static void
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xor_sse_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3, unsigned long *p4)
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{
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unsigned int lines = bytes >> 8;
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xmm_store_t xmm_save[4];
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unsigned long cr0;
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XMMS_SAVE;
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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PF1(i) \
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PF1(i + 2) \
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LD(i, 0) \
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LD(i + 1, 1) \
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LD(i + 2, 2) \
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LD(i + 3, 3) \
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PF2(i) \
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PF2(i + 2) \
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XO1(i, 0) \
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XO1(i + 1, 1) \
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XO1(i + 2, 2) \
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XO1(i + 3, 3) \
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PF3(i) \
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PF3(i + 2) \
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PF0(i + 4) \
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PF0(i + 6) \
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XO2(i, 0) \
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XO2(i + 1, 1) \
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XO2(i + 2, 2) \
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XO2(i + 3, 3) \
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XO3(i, 0) \
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XO3(i + 1, 1) \
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XO3(i + 2, 2) \
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XO3(i + 3, 3) \
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ST(i, 0) \
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ST(i + 1, 1) \
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ST(i + 2, 2) \
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ST(i + 3, 3) \
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PF0(0)
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PF0(2)
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" addq %[inc], %[p1] ;\n"
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" addq %[inc], %[p2] ;\n"
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" addq %[inc], %[p3] ;\n"
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" addq %[inc], %[p4] ;\n"
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" decl %[cnt] ; jnz 1b"
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: [cnt] "+c" (lines),
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[p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3), [p4] "+r" (p4)
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: [inc] "r" (256UL)
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: "memory" );
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XMMS_RESTORE;
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}
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static void
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xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3, unsigned long *p4, unsigned long *p5)
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{
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unsigned int lines = bytes >> 8;
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xmm_store_t xmm_save[4];
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unsigned long cr0;
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XMMS_SAVE;
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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PF1(i) \
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PF1(i + 2) \
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LD(i, 0) \
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LD(i + 1, 1) \
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LD(i + 2, 2) \
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LD(i + 3, 3) \
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PF2(i) \
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PF2(i + 2) \
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XO1(i, 0) \
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XO1(i + 1, 1) \
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XO1(i + 2, 2) \
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XO1(i + 3, 3) \
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PF3(i) \
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PF3(i + 2) \
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XO2(i, 0) \
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XO2(i + 1, 1) \
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XO2(i + 2, 2) \
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XO2(i + 3, 3) \
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PF4(i) \
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PF4(i + 2) \
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PF0(i + 4) \
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PF0(i + 6) \
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XO3(i, 0) \
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XO3(i + 1, 1) \
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XO3(i + 2, 2) \
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XO3(i + 3, 3) \
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XO4(i, 0) \
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XO4(i + 1, 1) \
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XO4(i + 2, 2) \
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XO4(i + 3, 3) \
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ST(i, 0) \
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ST(i + 1, 1) \
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ST(i + 2, 2) \
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ST(i + 3, 3) \
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PF0(0)
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PF0(2)
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" addq %[inc], %[p1] ;\n"
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" addq %[inc], %[p2] ;\n"
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" addq %[inc], %[p3] ;\n"
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" addq %[inc], %[p4] ;\n"
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" addq %[inc], %[p5] ;\n"
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" decl %[cnt] ; jnz 1b"
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: [cnt] "+c" (lines),
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[p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3), [p4] "+r" (p4),
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[p5] "+r" (p5)
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: [inc] "r" (256UL)
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: "memory");
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XMMS_RESTORE;
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}
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static struct xor_block_template xor_block_sse = {
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.name = "generic_sse",
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.do_2 = xor_sse_2,
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.do_3 = xor_sse_3,
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.do_4 = xor_sse_4,
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.do_5 = xor_sse_5,
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};
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#undef XOR_TRY_TEMPLATES
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#define XOR_TRY_TEMPLATES \
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do { \
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xor_speed(&xor_block_sse); \
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} while (0)
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/* We force the use of the SSE xor block because it can write around L2.
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We may also be able to load into the L1 only depending on how the cpu
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deals with a load to a line that is being prefetched. */
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#define XOR_SELECT_TEMPLATE(FASTEST) (&xor_block_sse)
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#endif /* _ASM_X86_XOR_64_H */
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