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https://github.com/edk2-porting/linux-next.git
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d695bfd6f0
These are going to be required by the addition of the GCM support. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
175 lines
4.5 KiB
C
175 lines
4.5 KiB
C
/*
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* Cryptographic API.
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*
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* Support for OMAP AES HW ACCELERATOR defines
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*
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* Copyright (c) 2015 Texas Instruments Incorporated
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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*/
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#ifndef __OMAP_AES_H__
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#define __OMAP_AES_H__
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#define DST_MAXBURST 4
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#define DMA_MIN (DST_MAXBURST * sizeof(u32))
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#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
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/*
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* OMAP TRM gives bitfields as start:end, where start is the higher bit
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* number. For example 7:0
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*/
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#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
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#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
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#define AES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
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(((x) ^ 0x01) * 0x04))
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#define AES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
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#define AES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
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#define AES_REG_CTRL_CTR_WIDTH_MASK GENMASK(8, 7)
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#define AES_REG_CTRL_CTR_WIDTH_32 0
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#define AES_REG_CTRL_CTR_WIDTH_64 BIT(7)
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#define AES_REG_CTRL_CTR_WIDTH_96 BIT(8)
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#define AES_REG_CTRL_CTR_WIDTH_128 GENMASK(8, 7)
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#define AES_REG_CTRL_CTR BIT(6)
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#define AES_REG_CTRL_CBC BIT(5)
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#define AES_REG_CTRL_KEY_SIZE GENMASK(4, 3)
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#define AES_REG_CTRL_DIRECTION BIT(2)
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#define AES_REG_CTRL_INPUT_READY BIT(1)
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#define AES_REG_CTRL_OUTPUT_READY BIT(0)
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#define AES_REG_CTRL_MASK GENMASK(24, 2)
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#define AES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
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#define AES_REG_REV(dd) ((dd)->pdata->rev_ofs)
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#define AES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
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#define AES_REG_MASK_SIDLE BIT(6)
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#define AES_REG_MASK_START BIT(5)
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#define AES_REG_MASK_DMA_OUT_EN BIT(3)
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#define AES_REG_MASK_DMA_IN_EN BIT(2)
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#define AES_REG_MASK_SOFTRESET BIT(1)
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#define AES_REG_AUTOIDLE BIT(0)
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#define AES_REG_LENGTH_N(x) (0x54 + ((x) * 0x04))
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#define AES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
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#define AES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
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#define AES_REG_IRQ_DATA_IN BIT(1)
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#define AES_REG_IRQ_DATA_OUT BIT(2)
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#define DEFAULT_TIMEOUT (5 * HZ)
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#define DEFAULT_AUTOSUSPEND_DELAY 1000
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#define FLAGS_MODE_MASK 0x000f
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#define FLAGS_ENCRYPT BIT(0)
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#define FLAGS_CBC BIT(1)
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#define FLAGS_GIV BIT(2)
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#define FLAGS_CTR BIT(3)
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#define FLAGS_INIT BIT(4)
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#define FLAGS_FAST BIT(5)
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#define FLAGS_BUSY BIT(6)
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#define FLAGS_IN_DATA_ST_SHIFT 8
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#define FLAGS_OUT_DATA_ST_SHIFT 10
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#define AES_BLOCK_WORDS (AES_BLOCK_SIZE >> 2)
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struct omap_aes_ctx {
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int keylen;
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u32 key[AES_KEYSIZE_256 / sizeof(u32)];
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struct crypto_skcipher *fallback;
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};
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struct omap_aes_reqctx {
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struct omap_aes_dev *dd;
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unsigned long mode;
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};
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#define OMAP_AES_QUEUE_LENGTH 1
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#define OMAP_AES_CACHE_SIZE 0
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struct omap_aes_algs_info {
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struct crypto_alg *algs_list;
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unsigned int size;
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unsigned int registered;
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};
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struct omap_aes_pdata {
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struct omap_aes_algs_info *algs_info;
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unsigned int algs_info_size;
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void (*trigger)(struct omap_aes_dev *dd, int length);
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u32 key_ofs;
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u32 iv_ofs;
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u32 ctrl_ofs;
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u32 data_ofs;
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u32 rev_ofs;
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u32 mask_ofs;
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u32 irq_enable_ofs;
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u32 irq_status_ofs;
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u32 dma_enable_in;
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u32 dma_enable_out;
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u32 dma_start;
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u32 major_mask;
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u32 major_shift;
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u32 minor_mask;
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u32 minor_shift;
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};
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struct omap_aes_dev {
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struct list_head list;
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unsigned long phys_base;
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void __iomem *io_base;
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struct omap_aes_ctx *ctx;
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struct device *dev;
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unsigned long flags;
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int err;
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struct tasklet_struct done_task;
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struct ablkcipher_request *req;
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struct crypto_engine *engine;
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/*
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* total is used by PIO mode for book keeping so introduce
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* variable total_save as need it to calc page_order
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*/
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size_t total;
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size_t total_save;
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struct scatterlist *in_sg;
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struct scatterlist *out_sg;
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/* Buffers for copying for unaligned cases */
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struct scatterlist in_sgl;
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struct scatterlist out_sgl;
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struct scatterlist *orig_out;
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struct scatter_walk in_walk;
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struct scatter_walk out_walk;
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struct dma_chan *dma_lch_in;
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struct dma_chan *dma_lch_out;
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int in_sg_len;
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int out_sg_len;
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int pio_only;
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const struct omap_aes_pdata *pdata;
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};
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u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset);
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void omap_aes_write(struct omap_aes_dev *dd, u32 offset, u32 value);
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struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx);
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int omap_aes_write_ctrl(struct omap_aes_dev *dd);
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int omap_aes_crypt_dma_start(struct omap_aes_dev *dd);
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int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd);
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#endif
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