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fd73351943
Describe the location and contents of the SYSCEXTMASK register on R-Car M3-N, to prevent conflicts between internal and external power requests. Based on a patch in the BSP by Dien Pham <dien.pham.ry@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190828113618.6672-5-geert+renesas@glider.be
40 lines
1.3 KiB
C
40 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas R-Car M3-N System Controller
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* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
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*
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* Based on Renesas R-Car M3-W System Controller
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* Copyright (C) 2016 Glider bvba
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*/
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#include <linux/bits.h>
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <dt-bindings/power/r8a77965-sysc.h>
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#include "rcar-sysc.h"
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static const struct rcar_sysc_area r8a77965_areas[] __initconst = {
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{ "always-on", 0, 0, R8A77965_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
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{ "ca57-scu", 0x1c0, 0, R8A77965_PD_CA57_SCU, R8A77965_PD_ALWAYS_ON,
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PD_SCU },
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{ "ca57-cpu0", 0x80, 0, R8A77965_PD_CA57_CPU0, R8A77965_PD_CA57_SCU,
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PD_CPU_NOCR },
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{ "ca57-cpu1", 0x80, 1, R8A77965_PD_CA57_CPU1, R8A77965_PD_CA57_SCU,
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PD_CPU_NOCR },
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{ "cr7", 0x240, 0, R8A77965_PD_CR7, R8A77965_PD_ALWAYS_ON },
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{ "a3vc", 0x380, 0, R8A77965_PD_A3VC, R8A77965_PD_ALWAYS_ON },
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{ "a3vp", 0x340, 0, R8A77965_PD_A3VP, R8A77965_PD_ALWAYS_ON },
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{ "a2vc1", 0x3c0, 1, R8A77965_PD_A2VC1, R8A77965_PD_A3VC },
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{ "3dg-a", 0x100, 0, R8A77965_PD_3DG_A, R8A77965_PD_ALWAYS_ON },
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{ "3dg-b", 0x100, 1, R8A77965_PD_3DG_B, R8A77965_PD_3DG_A },
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};
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const struct rcar_sysc_info r8a77965_sysc_info __initconst = {
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.areas = r8a77965_areas,
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.num_areas = ARRAY_SIZE(r8a77965_areas),
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.extmask_offs = 0x2f8,
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.extmask_val = BIT(0),
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};
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