mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 05:34:00 +08:00
11964f53eb
should now boot on mainline after this is applied, according to Vaibhav. This second version includes trailing commas at the end of structure records at Tony's request. It also adds a OMAP_INTC_START macro expansion to each IRQ number to make the sparseirq conversion easier. Basic build, boot, and PM test transcripts are here: http://www.pwsan.com/omap/testlogs/am33xx_hwmod_clock_devel_3.7/20120912165952/ -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJQURsaAAoJEMePsQ0LvSpLl24QAIMeCOw7z+SEjOetmWPRekS6 uPj9mz7EkWjBITMAPToQ7v9oESn+M0jcaD7wkOKaVBhPj6shXUwaMy6KmcZ5BuKf 1zrjL57ljhVLYumX8sKO3vPfKt1JvRCvcgu7xtgDKc9ywmuJLqolbi9BNxh/xo94 7IQHJk6Snrz6DxRTcvX2jUOwHG5o8WCGjPST5ZTQCKQKdpxKyeUILrhddbJMQdaq U7DTxZVdk75KM0dbt8wVRP7AWczh8TLBEKR/bsWF47g/iL0neMDuLXyfrOd0A5ct +JyGycl5a6lF/TiTQ7Is36s0uquidKozIx+2PwCdJGX/ntvme1wOZUGq1NSET/sw /Uos1NjJqhM1wLPL0AbuJ8hQlZkvZThYL6c0a+GSxKGKE2dtk5ZH8vC/JMv17u21 RUzxjq1rDZVGYnm3CtO305kzQYxdUu/7aBMCE29gWKrlPr8Pz2O6wvkFePja9Qxe YmlxakogwpFkmMaQ3eeN14VEuXCd7c2i1o8XiF/9ph250qzzKd6wTSra6Xggd32L 17GXtAfGWySqgFhb3Mfupbbr/lWGSFLeW2NhT7ZGsORvTC8J4KCql0r7f9V0/1WH DjUcljoYF15CdOxh71vIsUOKDqN0RtyRIgeBXaIam8RDNhaF5WJjjtiIbFIS4EAm Xw9zTjalQzJnbivxz/cy =yRjp -----END PGP SIGNATURE----- Merge tag 'omap-devel-a2-for-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-am33xx AM33xx hwmod data and miscellaneous clock and hwmod fixes. AM33xx should now boot on mainline after this is applied, according to Vaibhav. This second version includes trailing commas at the end of structure records at Tony's request. It also adds a OMAP_INTC_START macro expansion to each IRQ number to make the sparseirq conversion easier. Basic build, boot, and PM test transcripts are here: http://www.pwsan.com/omap/testlogs/am33xx_hwmod_clock_devel_3.7/20120912165952/
575 lines
12 KiB
C
575 lines
12 KiB
C
/*
|
|
* linux/arch/arm/mach-omap2/io.c
|
|
*
|
|
* OMAP2 I/O mapping code
|
|
*
|
|
* Copyright (C) 2005 Nokia Corporation
|
|
* Copyright (C) 2007-2009 Texas Instruments
|
|
*
|
|
* Author:
|
|
* Juha Yrjola <juha.yrjola@nokia.com>
|
|
* Syed Khasim <x0khasim@ti.com>
|
|
*
|
|
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
#include <linux/module.h>
|
|
#include <linux/kernel.h>
|
|
#include <linux/init.h>
|
|
#include <linux/io.h>
|
|
#include <linux/clk.h>
|
|
|
|
#include <asm/tlb.h>
|
|
#include <asm/mach/map.h>
|
|
|
|
#include <plat/sram.h>
|
|
#include <plat/sdrc.h>
|
|
#include <plat/serial.h>
|
|
#include <plat/omap-pm.h>
|
|
#include <plat/omap_hwmod.h>
|
|
#include <plat/multi.h>
|
|
#include <plat/dma.h>
|
|
|
|
#include "soc.h"
|
|
#include "iomap.h"
|
|
#include "voltage.h"
|
|
#include "powerdomain.h"
|
|
#include "clockdomain.h"
|
|
#include "common.h"
|
|
#include "clock.h"
|
|
#include "clock2xxx.h"
|
|
#include "clock3xxx.h"
|
|
#include "clock44xx.h"
|
|
|
|
/*
|
|
* The machine specific code may provide the extra mapping besides the
|
|
* default mapping provided here.
|
|
*/
|
|
|
|
#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
|
|
static struct map_desc omap24xx_io_desc[] __initdata = {
|
|
{
|
|
.virtual = L3_24XX_VIRT,
|
|
.pfn = __phys_to_pfn(L3_24XX_PHYS),
|
|
.length = L3_24XX_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = L4_24XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_24XX_PHYS),
|
|
.length = L4_24XX_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
};
|
|
|
|
#ifdef CONFIG_SOC_OMAP2420
|
|
static struct map_desc omap242x_io_desc[] __initdata = {
|
|
{
|
|
.virtual = DSP_MEM_2420_VIRT,
|
|
.pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
|
|
.length = DSP_MEM_2420_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = DSP_IPI_2420_VIRT,
|
|
.pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
|
|
.length = DSP_IPI_2420_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = DSP_MMU_2420_VIRT,
|
|
.pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
|
|
.length = DSP_MMU_2420_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
};
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_OMAP2430
|
|
static struct map_desc omap243x_io_desc[] __initdata = {
|
|
{
|
|
.virtual = L4_WK_243X_VIRT,
|
|
.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
|
|
.length = L4_WK_243X_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = OMAP243X_GPMC_VIRT,
|
|
.pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
|
|
.length = OMAP243X_GPMC_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = OMAP243X_SDRC_VIRT,
|
|
.pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
|
|
.length = OMAP243X_SDRC_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = OMAP243X_SMS_VIRT,
|
|
.pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
|
|
.length = OMAP243X_SMS_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
};
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
static struct map_desc omap34xx_io_desc[] __initdata = {
|
|
{
|
|
.virtual = L3_34XX_VIRT,
|
|
.pfn = __phys_to_pfn(L3_34XX_PHYS),
|
|
.length = L3_34XX_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = L4_34XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_34XX_PHYS),
|
|
.length = L4_34XX_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = OMAP34XX_GPMC_VIRT,
|
|
.pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
|
|
.length = OMAP34XX_GPMC_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = OMAP343X_SMS_VIRT,
|
|
.pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
|
|
.length = OMAP343X_SMS_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = OMAP343X_SDRC_VIRT,
|
|
.pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
|
|
.length = OMAP343X_SDRC_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = L4_PER_34XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
|
|
.length = L4_PER_34XX_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = L4_EMU_34XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
|
|
.length = L4_EMU_34XX_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
#if defined(CONFIG_DEBUG_LL) && \
|
|
(defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
|
|
{
|
|
.virtual = ZOOM_UART_VIRT,
|
|
.pfn = __phys_to_pfn(ZOOM_UART_BASE),
|
|
.length = SZ_1M,
|
|
.type = MT_DEVICE
|
|
},
|
|
#endif
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_TI81XX
|
|
static struct map_desc omapti81xx_io_desc[] __initdata = {
|
|
{
|
|
.virtual = L4_34XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_34XX_PHYS),
|
|
.length = L4_34XX_SIZE,
|
|
.type = MT_DEVICE
|
|
}
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_AM33XX
|
|
static struct map_desc omapam33xx_io_desc[] __initdata = {
|
|
{
|
|
.virtual = L4_34XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_34XX_PHYS),
|
|
.length = L4_34XX_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = L4_WK_AM33XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
|
|
.length = L4_WK_AM33XX_SIZE,
|
|
.type = MT_DEVICE
|
|
}
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
static struct map_desc omap44xx_io_desc[] __initdata = {
|
|
{
|
|
.virtual = L3_44XX_VIRT,
|
|
.pfn = __phys_to_pfn(L3_44XX_PHYS),
|
|
.length = L3_44XX_SIZE,
|
|
.type = MT_DEVICE,
|
|
},
|
|
{
|
|
.virtual = L4_44XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_44XX_PHYS),
|
|
.length = L4_44XX_SIZE,
|
|
.type = MT_DEVICE,
|
|
},
|
|
{
|
|
.virtual = L4_PER_44XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
|
|
.length = L4_PER_44XX_SIZE,
|
|
.type = MT_DEVICE,
|
|
},
|
|
#ifdef CONFIG_OMAP4_ERRATA_I688
|
|
{
|
|
.virtual = OMAP4_SRAM_VA,
|
|
.pfn = __phys_to_pfn(OMAP4_SRAM_PA),
|
|
.length = PAGE_SIZE,
|
|
.type = MT_MEMORY_SO,
|
|
},
|
|
#endif
|
|
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_OMAP5
|
|
static struct map_desc omap54xx_io_desc[] __initdata = {
|
|
{
|
|
.virtual = L3_54XX_VIRT,
|
|
.pfn = __phys_to_pfn(L3_54XX_PHYS),
|
|
.length = L3_54XX_SIZE,
|
|
.type = MT_DEVICE,
|
|
},
|
|
{
|
|
.virtual = L4_54XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_54XX_PHYS),
|
|
.length = L4_54XX_SIZE,
|
|
.type = MT_DEVICE,
|
|
},
|
|
{
|
|
.virtual = L4_WK_54XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
|
|
.length = L4_WK_54XX_SIZE,
|
|
.type = MT_DEVICE,
|
|
},
|
|
{
|
|
.virtual = L4_PER_54XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
|
|
.length = L4_PER_54XX_SIZE,
|
|
.type = MT_DEVICE,
|
|
},
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_OMAP2420
|
|
void __init omap242x_map_common_io(void)
|
|
{
|
|
iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
|
|
iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_OMAP2430
|
|
void __init omap243x_map_common_io(void)
|
|
{
|
|
iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
|
|
iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
void __init omap34xx_map_common_io(void)
|
|
{
|
|
iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_TI81XX
|
|
void __init omapti81xx_map_common_io(void)
|
|
{
|
|
iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_AM33XX
|
|
void __init omapam33xx_map_common_io(void)
|
|
{
|
|
iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
void __init omap44xx_map_common_io(void)
|
|
{
|
|
iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
|
|
omap_barriers_init();
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_OMAP5
|
|
void __init omap5_map_common_io(void)
|
|
{
|
|
iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
|
|
}
|
|
#endif
|
|
/*
|
|
* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
|
|
*
|
|
* Sets the CORE DPLL3 M2 divider to the same value that it's at
|
|
* currently. This has the effect of setting the SDRC SDRAM AC timing
|
|
* registers to the values currently defined by the kernel. Currently
|
|
* only defined for OMAP3; will return 0 if called on OMAP2. Returns
|
|
* -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
|
|
* or passes along the return value of clk_set_rate().
|
|
*/
|
|
static int __init _omap2_init_reprogram_sdrc(void)
|
|
{
|
|
struct clk *dpll3_m2_ck;
|
|
int v = -EINVAL;
|
|
long rate;
|
|
|
|
if (!cpu_is_omap34xx())
|
|
return 0;
|
|
|
|
dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
|
|
if (IS_ERR(dpll3_m2_ck))
|
|
return -EINVAL;
|
|
|
|
rate = clk_get_rate(dpll3_m2_ck);
|
|
pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
|
|
v = clk_set_rate(dpll3_m2_ck, rate);
|
|
if (v)
|
|
pr_err("dpll3_m2_clk rate change failed: %d\n", v);
|
|
|
|
clk_put(dpll3_m2_ck);
|
|
|
|
return v;
|
|
}
|
|
|
|
static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
|
|
{
|
|
return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
|
|
}
|
|
|
|
static void __init omap_common_init_early(void)
|
|
{
|
|
omap_init_consistent_dma_size();
|
|
}
|
|
|
|
static void __init omap_hwmod_init_postsetup(void)
|
|
{
|
|
u8 postsetup_state;
|
|
|
|
/* Set the default postsetup state for all hwmods */
|
|
#ifdef CONFIG_PM_RUNTIME
|
|
postsetup_state = _HWMOD_STATE_IDLE;
|
|
#else
|
|
postsetup_state = _HWMOD_STATE_ENABLED;
|
|
#endif
|
|
omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
|
|
|
|
omap_pm_if_early_init();
|
|
}
|
|
|
|
#ifdef CONFIG_SOC_OMAP2420
|
|
void __init omap2420_init_early(void)
|
|
{
|
|
omap2_set_globals_242x();
|
|
omap2xxx_check_revision();
|
|
omap_common_init_early();
|
|
omap2xxx_voltagedomains_init();
|
|
omap242x_powerdomains_init();
|
|
omap242x_clockdomains_init();
|
|
omap2420_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap2420_clk_init();
|
|
}
|
|
|
|
void __init omap2420_init_late(void)
|
|
{
|
|
omap_mux_late_init();
|
|
omap2_common_pm_late_init();
|
|
omap2_pm_init();
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_OMAP2430
|
|
void __init omap2430_init_early(void)
|
|
{
|
|
omap2_set_globals_243x();
|
|
omap2xxx_check_revision();
|
|
omap_common_init_early();
|
|
omap2xxx_voltagedomains_init();
|
|
omap243x_powerdomains_init();
|
|
omap243x_clockdomains_init();
|
|
omap2430_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap2430_clk_init();
|
|
}
|
|
|
|
void __init omap2430_init_late(void)
|
|
{
|
|
omap_mux_late_init();
|
|
omap2_common_pm_late_init();
|
|
omap2_pm_init();
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Currently only board-omap3beagle.c should call this because of the
|
|
* same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
|
|
*/
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
void __init omap3_init_early(void)
|
|
{
|
|
omap2_set_globals_3xxx();
|
|
omap3xxx_check_revision();
|
|
omap3xxx_check_features();
|
|
omap_common_init_early();
|
|
omap3xxx_voltagedomains_init();
|
|
omap3xxx_powerdomains_init();
|
|
omap3xxx_clockdomains_init();
|
|
omap3xxx_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap3xxx_clk_init();
|
|
}
|
|
|
|
void __init omap3430_init_early(void)
|
|
{
|
|
omap3_init_early();
|
|
}
|
|
|
|
void __init omap35xx_init_early(void)
|
|
{
|
|
omap3_init_early();
|
|
}
|
|
|
|
void __init omap3630_init_early(void)
|
|
{
|
|
omap3_init_early();
|
|
}
|
|
|
|
void __init am35xx_init_early(void)
|
|
{
|
|
omap3_init_early();
|
|
}
|
|
|
|
void __init ti81xx_init_early(void)
|
|
{
|
|
omap2_set_globals_ti81xx();
|
|
omap3xxx_check_revision();
|
|
ti81xx_check_features();
|
|
omap_common_init_early();
|
|
omap3xxx_voltagedomains_init();
|
|
omap3xxx_powerdomains_init();
|
|
omap3xxx_clockdomains_init();
|
|
omap3xxx_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap3xxx_clk_init();
|
|
}
|
|
|
|
void __init omap3_init_late(void)
|
|
{
|
|
omap_mux_late_init();
|
|
omap2_common_pm_late_init();
|
|
omap3_pm_init();
|
|
}
|
|
|
|
void __init omap3430_init_late(void)
|
|
{
|
|
omap_mux_late_init();
|
|
omap2_common_pm_late_init();
|
|
omap3_pm_init();
|
|
}
|
|
|
|
void __init omap35xx_init_late(void)
|
|
{
|
|
omap_mux_late_init();
|
|
omap2_common_pm_late_init();
|
|
omap3_pm_init();
|
|
}
|
|
|
|
void __init omap3630_init_late(void)
|
|
{
|
|
omap_mux_late_init();
|
|
omap2_common_pm_late_init();
|
|
omap3_pm_init();
|
|
}
|
|
|
|
void __init am35xx_init_late(void)
|
|
{
|
|
omap_mux_late_init();
|
|
omap2_common_pm_late_init();
|
|
omap3_pm_init();
|
|
}
|
|
|
|
void __init ti81xx_init_late(void)
|
|
{
|
|
omap_mux_late_init();
|
|
omap2_common_pm_late_init();
|
|
omap3_pm_init();
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_AM33XX
|
|
void __init am33xx_init_early(void)
|
|
{
|
|
omap2_set_globals_am33xx();
|
|
omap3xxx_check_revision();
|
|
ti81xx_check_features();
|
|
omap_common_init_early();
|
|
am33xx_voltagedomains_init();
|
|
am33xx_powerdomains_init();
|
|
am33xx_clockdomains_init();
|
|
am33xx_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
am33xx_clk_init();
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
void __init omap4430_init_early(void)
|
|
{
|
|
omap2_set_globals_443x();
|
|
omap4xxx_check_revision();
|
|
omap4xxx_check_features();
|
|
omap_common_init_early();
|
|
omap44xx_voltagedomains_init();
|
|
omap44xx_powerdomains_init();
|
|
omap44xx_clockdomains_init();
|
|
omap44xx_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap4xxx_clk_init();
|
|
}
|
|
|
|
void __init omap4430_init_late(void)
|
|
{
|
|
omap_mux_late_init();
|
|
omap2_common_pm_late_init();
|
|
omap4_pm_init();
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_OMAP5
|
|
void __init omap5_init_early(void)
|
|
{
|
|
omap2_set_globals_5xxx();
|
|
omap5xxx_check_revision();
|
|
omap_common_init_early();
|
|
}
|
|
#endif
|
|
|
|
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
|
|
struct omap_sdrc_params *sdrc_cs1)
|
|
{
|
|
omap_sram_init();
|
|
|
|
if (cpu_is_omap24xx() || omap3_has_sdrc()) {
|
|
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
|
|
_omap2_init_reprogram_sdrc();
|
|
}
|
|
}
|