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d51dc91761
Check demod and ts locks and report lock status according to those. Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
351 lines
7.9 KiB
C
351 lines
7.9 KiB
C
/*
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* Sony CXD2820R demodulator driver
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*
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* Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "cxd2820r_priv.h"
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int cxd2820r_set_frontend_c(struct dvb_frontend *fe)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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struct i2c_client *client = priv->client[0];
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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int ret, i;
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unsigned int utmp;
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u8 buf[2];
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u32 if_frequency;
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struct reg_val_mask tab[] = {
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{ 0x00080, 0x01, 0xff },
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{ 0x00081, 0x05, 0xff },
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{ 0x00085, 0x07, 0xff },
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{ 0x00088, 0x01, 0xff },
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{ 0x00082, 0x20, 0x60 },
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{ 0x1016a, 0x48, 0xff },
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{ 0x100a5, 0x00, 0x01 },
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{ 0x10020, 0x06, 0x07 },
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{ 0x10059, 0x50, 0xff },
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{ 0x10087, 0x0c, 0x3c },
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{ 0x1008b, 0x07, 0xff },
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{ 0x1001f, priv->if_agc_polarity << 7, 0x80 },
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{ 0x10070, priv->ts_mode, 0xff },
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{ 0x10071, !priv->ts_clk_inv << 4, 0x10 },
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};
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dev_dbg(&client->dev,
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"delivery_system=%d modulation=%d frequency=%u symbol_rate=%u inversion=%d\n",
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c->delivery_system, c->modulation, c->frequency,
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c->symbol_rate, c->inversion);
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/* program tuner */
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if (fe->ops.tuner_ops.set_params)
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fe->ops.tuner_ops.set_params(fe);
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if (priv->delivery_system != SYS_DVBC_ANNEX_A) {
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for (i = 0; i < ARRAY_SIZE(tab); i++) {
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ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
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tab[i].val, tab[i].mask);
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if (ret)
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goto error;
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}
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}
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priv->delivery_system = SYS_DVBC_ANNEX_A;
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priv->ber_running = false; /* tune stops BER counter */
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/* program IF frequency */
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if (fe->ops.tuner_ops.get_if_frequency) {
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ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
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if (ret)
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goto error;
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dev_dbg(&client->dev, "if_frequency=%u\n", if_frequency);
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} else {
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ret = -EINVAL;
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goto error;
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}
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utmp = 0x4000 - DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x4000, CXD2820R_CLK);
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buf[0] = (utmp >> 8) & 0xff;
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buf[1] = (utmp >> 0) & 0xff;
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ret = cxd2820r_wr_regs(priv, 0x10042, buf, 2);
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if (ret)
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goto error;
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ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);
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if (ret)
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goto error;
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ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);
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if (ret)
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goto error;
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return ret;
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error:
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dev_dbg(&client->dev, "failed=%d\n", ret);
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return ret;
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}
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int cxd2820r_get_frontend_c(struct dvb_frontend *fe,
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struct dtv_frontend_properties *c)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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struct i2c_client *client = priv->client[0];
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int ret;
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u8 buf[2];
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dev_dbg(&client->dev, "\n");
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ret = cxd2820r_rd_regs(priv, 0x1001a, buf, 2);
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if (ret)
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goto error;
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c->symbol_rate = 2500 * ((buf[0] & 0x0f) << 8 | buf[1]);
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ret = cxd2820r_rd_reg(priv, 0x10019, &buf[0]);
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if (ret)
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goto error;
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switch ((buf[0] >> 0) & 0x07) {
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case 0:
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c->modulation = QAM_16;
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break;
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case 1:
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c->modulation = QAM_32;
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break;
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case 2:
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c->modulation = QAM_64;
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break;
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case 3:
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c->modulation = QAM_128;
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break;
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case 4:
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c->modulation = QAM_256;
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break;
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}
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switch ((buf[0] >> 7) & 0x01) {
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case 0:
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c->inversion = INVERSION_OFF;
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break;
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case 1:
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c->inversion = INVERSION_ON;
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break;
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}
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return ret;
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error:
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dev_dbg(&client->dev, "failed=%d\n", ret);
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return ret;
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}
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int cxd2820r_read_status_c(struct dvb_frontend *fe, enum fe_status *status)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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struct i2c_client *client = priv->client[0];
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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int ret;
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unsigned int utmp, utmp1, utmp2;
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u8 buf[3];
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/* Lock detection */
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ret = cxd2820r_rd_reg(priv, 0x10088, &buf[0]);
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if (ret)
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goto error;
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ret = cxd2820r_rd_reg(priv, 0x10073, &buf[1]);
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if (ret)
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goto error;
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utmp1 = (buf[0] >> 0) & 0x01;
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utmp2 = (buf[1] >> 3) & 0x01;
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if (utmp1 == 1 && utmp2 == 1) {
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*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
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FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
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} else if (utmp1 == 1 || utmp2 == 1) {
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*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
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FE_HAS_VITERBI | FE_HAS_SYNC;
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} else {
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*status = 0;
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}
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dev_dbg(&client->dev, "status=%02x raw=%*ph sync=%u ts=%u\n",
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*status, 2, buf, utmp1, utmp2);
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/* Signal strength */
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if (*status & FE_HAS_SIGNAL) {
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unsigned int strength;
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ret = cxd2820r_rd_regs(priv, 0x10049, buf, 2);
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if (ret)
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goto error;
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utmp = buf[0] << 8 | buf[1] << 0;
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utmp = 511 - sign_extend32(utmp, 9);
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/* Scale value to 0x0000-0xffff */
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strength = utmp << 6 | utmp >> 4;
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c->strength.len = 1;
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c->strength.stat[0].scale = FE_SCALE_RELATIVE;
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c->strength.stat[0].uvalue = strength;
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} else {
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c->strength.len = 1;
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c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
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}
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/* CNR */
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if (*status & FE_HAS_VITERBI) {
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unsigned int cnr, const_a, const_b;
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ret = cxd2820r_rd_reg(priv, 0x10019, &buf[0]);
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if (ret)
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goto error;
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if (((buf[0] >> 0) & 0x03) % 2) {
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const_a = 8750;
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const_b = 650;
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} else {
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const_a = 9500;
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const_b = 760;
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}
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ret = cxd2820r_rd_reg(priv, 0x1004d, &buf[0]);
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if (ret)
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goto error;
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utmp = buf[0] << 0;
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#define CXD2820R_LOG2_E_24 24204406 /* log2(e) << 24 */
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if (utmp)
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cnr = div_u64((u64)(intlog2(const_b) - intlog2(utmp))
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* const_a, CXD2820R_LOG2_E_24);
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else
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cnr = 0;
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c->cnr.len = 1;
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c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
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c->cnr.stat[0].svalue = cnr;
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} else {
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c->cnr.len = 1;
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c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
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}
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/* BER */
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if (*status & FE_HAS_SYNC) {
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unsigned int post_bit_error;
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bool start_ber;
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if (priv->ber_running) {
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ret = cxd2820r_rd_regs(priv, 0x10076, buf, 3);
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if (ret)
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goto error;
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if ((buf[2] >> 7) & 0x01) {
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post_bit_error = buf[2] << 16 | buf[1] << 8 |
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buf[0] << 0;
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post_bit_error &= 0x0fffff;
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start_ber = true;
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} else {
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post_bit_error = 0;
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start_ber = false;
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}
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} else {
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post_bit_error = 0;
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start_ber = true;
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}
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if (start_ber) {
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ret = cxd2820r_wr_reg(priv, 0x10079, 0x01);
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if (ret)
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goto error;
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priv->ber_running = true;
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}
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priv->post_bit_error += post_bit_error;
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c->post_bit_error.len = 1;
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c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
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c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
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} else {
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c->post_bit_error.len = 1;
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c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
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}
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return ret;
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error:
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dev_dbg(&client->dev, "failed=%d\n", ret);
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return ret;
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}
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int cxd2820r_init_c(struct dvb_frontend *fe)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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struct i2c_client *client = priv->client[0];
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int ret;
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dev_dbg(&client->dev, "\n");
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ret = cxd2820r_wr_reg(priv, 0x00085, 0x07);
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if (ret)
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goto error;
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return ret;
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error:
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dev_dbg(&client->dev, "failed=%d\n", ret);
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return ret;
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}
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int cxd2820r_sleep_c(struct dvb_frontend *fe)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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struct i2c_client *client = priv->client[0];
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int ret, i;
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struct reg_val_mask tab[] = {
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{ 0x000ff, 0x1f, 0xff },
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{ 0x00085, 0x00, 0xff },
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{ 0x00088, 0x01, 0xff },
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{ 0x00081, 0x00, 0xff },
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{ 0x00080, 0x00, 0xff },
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};
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dev_dbg(&client->dev, "\n");
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priv->delivery_system = SYS_UNDEFINED;
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for (i = 0; i < ARRAY_SIZE(tab); i++) {
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ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,
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tab[i].mask);
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if (ret)
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goto error;
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}
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return ret;
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error:
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dev_dbg(&client->dev, "failed=%d\n", ret);
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return ret;
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}
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int cxd2820r_get_tune_settings_c(struct dvb_frontend *fe,
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struct dvb_frontend_tune_settings *s)
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{
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s->min_delay_ms = 500;
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s->step_size = 0; /* no zigzag */
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s->max_drift = 0;
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return 0;
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}
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