mirror of
https://github.com/edk2-porting/linux-next.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
134 lines
4.5 KiB
C
134 lines
4.5 KiB
C
/*
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* include/asm-v850/v850e_intc.h -- V850E CPU interrupt controller (INTC)
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*
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* Copyright (C) 2001,02,03 NEC Electronics Corporation
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* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#ifndef __V850_V850E_INTC_H__
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#define __V850_V850E_INTC_H__
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/* There are 4 16-bit `Interrupt Mask Registers' located contiguously
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starting from this base. Each interrupt uses a single bit to
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indicated enabled/disabled status. */
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#define V850E_INTC_IMR_BASE_ADDR 0xFFFFF100
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#define V850E_INTC_IMR_ADDR(irq) (V850E_INTC_IMR_BASE_ADDR + ((irq) >> 3))
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#define V850E_INTC_IMR_BIT(irq) ((irq) & 0x7)
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/* Each maskable interrupt has a single-byte control register at this
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address. */
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#define V850E_INTC_IC_BASE_ADDR 0xFFFFF110
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#define V850E_INTC_IC_ADDR(irq) (V850E_INTC_IC_BASE_ADDR + ((irq) << 1))
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#define V850E_INTC_IC(irq) (*(volatile u8 *)V850E_INTC_IC_ADDR(irq))
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/* Encode priority PR for storing in an interrupt control register. */
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#define V850E_INTC_IC_PR(pr) (pr)
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/* Interrupt disable bit in an interrupt control register. */
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#define V850E_INTC_IC_MK_BIT 6
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#define V850E_INTC_IC_MK (1 << V850E_INTC_IC_MK_BIT)
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/* Interrupt pending flag in an interrupt control register. */
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#define V850E_INTC_IC_IF_BIT 7
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#define V850E_INTC_IC_IF (1 << V850E_INTC_IC_IF_BIT)
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/* The ISPR (In-service priority register) contains one bit for each interrupt
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priority level, which is set to one when that level is currently being
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serviced (and thus blocking any interrupts of equal or lesser level). */
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#define V850E_INTC_ISPR_ADDR 0xFFFFF1FA
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#define V850E_INTC_ISPR (*(volatile u8 *)V850E_INTC_ISPR_ADDR)
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#ifndef __ASSEMBLY__
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/* Enable interrupt handling for interrupt IRQ. */
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static inline void v850e_intc_enable_irq (unsigned irq)
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{
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__asm__ __volatile__ ("clr1 %0, [%1]"
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:: "r" (V850E_INTC_IMR_BIT (irq)),
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"r" (V850E_INTC_IMR_ADDR (irq))
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: "memory");
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}
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/* Disable interrupt handling for interrupt IRQ. Note that any
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interrupts received while disabled will be delivered once the
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interrupt is enabled again, unless they are explicitly cleared using
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`v850e_intc_clear_pending_irq'. */
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static inline void v850e_intc_disable_irq (unsigned irq)
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{
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__asm__ __volatile__ ("set1 %0, [%1]"
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:: "r" (V850E_INTC_IMR_BIT (irq)),
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"r" (V850E_INTC_IMR_ADDR (irq))
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: "memory");
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}
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/* Return true if interrupt handling for interrupt IRQ is enabled. */
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static inline int v850e_intc_irq_enabled (unsigned irq)
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{
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int rval;
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__asm__ __volatile__ ("tst1 %1, [%2]; setf z, %0"
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: "=r" (rval)
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: "r" (V850E_INTC_IMR_BIT (irq)),
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"r" (V850E_INTC_IMR_ADDR (irq)));
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return rval;
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}
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/* Disable irqs from 0 until LIMIT. LIMIT must be a multiple of 8. */
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static inline void _v850e_intc_disable_irqs (unsigned limit)
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{
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unsigned long addr;
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for (addr = V850E_INTC_IMR_BASE_ADDR; limit >= 8; addr++, limit -= 8)
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*(char *)addr = 0xFF;
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}
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/* Disable all irqs. This is purposely a macro, because NUM_MACH_IRQS
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will be only be defined later. */
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#define v850e_intc_disable_irqs() _v850e_intc_disable_irqs (NUM_MACH_IRQS)
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/* Clear any pending interrupts for IRQ. */
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static inline void v850e_intc_clear_pending_irq (unsigned irq)
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{
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__asm__ __volatile__ ("clr1 %0, 0[%1]"
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:: "i" (V850E_INTC_IC_IF_BIT),
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"r" (V850E_INTC_IC_ADDR (irq))
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: "memory");
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}
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/* Return true if interrupt IRQ is pending (but disabled). */
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static inline int v850e_intc_irq_pending (unsigned irq)
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{
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int rval;
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__asm__ __volatile__ ("tst1 %1, 0[%2]; setf nz, %0"
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: "=r" (rval)
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: "i" (V850E_INTC_IC_IF_BIT),
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"r" (V850E_INTC_IC_ADDR (irq)));
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return rval;
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}
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struct v850e_intc_irq_init {
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const char *name; /* name of interrupt type */
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/* Range of kernel irq numbers for this type:
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BASE, BASE+INTERVAL, ..., BASE+INTERVAL*NUM */
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unsigned base, num, interval;
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unsigned priority; /* interrupt priority to assign */
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};
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struct hw_interrupt_type; /* fwd decl */
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/* Initialize HW_IRQ_TYPES for INTC-controlled irqs described in array
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INITS (which is terminated by an entry with the name field == 0). */
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extern void v850e_intc_init_irq_types (struct v850e_intc_irq_init *inits,
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struct hw_interrupt_type *hw_irq_types);
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#endif /* !__ASSEMBLY__ */
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#endif /* __V850_V850E_INTC_H__ */
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