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https://github.com/edk2-porting/linux-next.git
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784bdcd0aa
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
91 lines
2.9 KiB
C
91 lines
2.9 KiB
C
/*
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* Port on Texas Instruments TMS320C6x architecture
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*
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* Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated
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* Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_C6X_CACHE_H
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#define _ASM_C6X_CACHE_H
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#include <linux/irqflags.h>
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/*
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* Cache line size
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*/
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#define L1D_CACHE_BYTES 64
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#define L1P_CACHE_BYTES 32
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#define L2_CACHE_BYTES 128
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/*
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* L2 used as cache
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*/
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#define L2MODE_SIZE L2MODE_256K_CACHE
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/*
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* For practical reasons the L1_CACHE_BYTES defines should not be smaller than
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* the L2 line size
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*/
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#define L1_CACHE_BYTES L2_CACHE_BYTES
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#define L2_CACHE_ALIGN_LOW(x) \
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(((x) & ~(L2_CACHE_BYTES - 1)))
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#define L2_CACHE_ALIGN_UP(x) \
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(((x) + (L2_CACHE_BYTES - 1)) & ~(L2_CACHE_BYTES - 1))
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#define L2_CACHE_ALIGN_CNT(x) \
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(((x) + (sizeof(int) - 1)) & ~(sizeof(int) - 1))
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES
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/*
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* This is the granularity of hardware cacheability control.
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*/
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#define CACHEABILITY_ALIGN 0x01000000
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/*
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* Align a physical address to MAR regions
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*/
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#define CACHE_REGION_START(v) \
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(((u32) (v)) & ~(CACHEABILITY_ALIGN - 1))
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#define CACHE_REGION_END(v) \
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(((u32) (v) + (CACHEABILITY_ALIGN - 1)) & ~(CACHEABILITY_ALIGN - 1))
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extern void __init c6x_cache_init(void);
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extern void enable_caching(unsigned long start, unsigned long end);
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extern void disable_caching(unsigned long start, unsigned long end);
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extern void L1_cache_off(void);
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extern void L1_cache_on(void);
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extern void L1P_cache_global_invalidate(void);
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extern void L1D_cache_global_invalidate(void);
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extern void L1D_cache_global_writeback(void);
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extern void L1D_cache_global_writeback_invalidate(void);
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extern void L2_cache_set_mode(unsigned int mode);
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extern void L2_cache_global_writeback_invalidate(void);
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extern void L2_cache_global_writeback(void);
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extern void L1P_cache_block_invalidate(unsigned int start, unsigned int end);
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extern void L1D_cache_block_invalidate(unsigned int start, unsigned int end);
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extern void L1D_cache_block_writeback_invalidate(unsigned int start,
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unsigned int end);
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extern void L1D_cache_block_writeback(unsigned int start, unsigned int end);
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extern void L2_cache_block_invalidate(unsigned int start, unsigned int end);
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extern void L2_cache_block_writeback(unsigned int start, unsigned int end);
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extern void L2_cache_block_writeback_invalidate(unsigned int start,
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unsigned int end);
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extern void L2_cache_block_invalidate_nowait(unsigned int start,
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unsigned int end);
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extern void L2_cache_block_writeback_nowait(unsigned int start,
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unsigned int end);
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extern void L2_cache_block_writeback_invalidate_nowait(unsigned int start,
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unsigned int end);
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#endif /* _ASM_C6X_CACHE_H */
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