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d4d70aa596
When disabling the RPS interrupts there is a tricky dependency between the thread disabling the interrupts, the RPS interrupt handler and the corresponding RPS work. The RPS work can reenable the interrupts, so there is no straightforward order in the disabling thread to (1) make sure that any RPS work is flushed and to (2) disable all RPS interrupts. Currently this is solved by masking the interrupts using two separate mask registers (first level display IMR and PM IMR) and doing the disabling when all first level interrupts are disabled. This works, but the requirement to run with all first level interrupts disabled is unnecessary making the suspend / unload time ordering of RPS disabling wrt. other unitialization steps difficult and error prone. Removing this restriction allows us to disable RPS early during suspend / unload and forget about it for the rest of the sequence. By adding a more explicit method for avoiding the above race, it also becomes easier to prove its correctness. Finally currently we can hit the WARN in snb_update_pm_irq(), when a final RPS work runs with the first level interrupts already disabled. This won't lead to any problem (due to the separate interrupt masks), but with the change in this and the next patch we can get rid of the WARN, while leaving it in place for other scenarios. To address the above points, add a new RPS interrupts_enabled flag and use this during RPS disabling to avoid requeuing the RPS work and reenabling of the RPS interrupts. Since the interrupt disabling happens now in intel_suspend_gt_powersave(), we will disable RPS interrupts explicitly during suspend (and not just through the first level mask), but there is no problem doing so, it's also more consistent and allows us to unify more of the RPS disabling during suspend and unload time in the next patch. v2/v3: - rebase on patch "drm/i915: move rps irq disable one level up" in the patchset Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
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| .. | ||
| dvo_ch7xxx.c | ||
| dvo_ch7017.c | ||
| dvo_ivch.c | ||
| dvo_ns2501.c | ||
| dvo_sil164.c | ||
| dvo_tfp410.c | ||
| dvo.h | ||
| i915_cmd_parser.c | ||
| i915_debugfs.c | ||
| i915_dma.c | ||
| i915_drv.c | ||
| i915_drv.h | ||
| i915_gem_context.c | ||
| i915_gem_debug.c | ||
| i915_gem_dmabuf.c | ||
| i915_gem_evict.c | ||
| i915_gem_execbuffer.c | ||
| i915_gem_gtt.c | ||
| i915_gem_gtt.h | ||
| i915_gem_render_state.c | ||
| i915_gem_render_state.h | ||
| i915_gem_stolen.c | ||
| i915_gem_tiling.c | ||
| i915_gem_userptr.c | ||
| i915_gem.c | ||
| i915_gpu_error.c | ||
| i915_ioc32.c | ||
| i915_irq.c | ||
| i915_params.c | ||
| i915_reg.h | ||
| i915_suspend.c | ||
| i915_sysfs.c | ||
| i915_trace_points.c | ||
| i915_trace.h | ||
| i915_ums.c | ||
| intel_acpi.c | ||
| intel_audio.c | ||
| intel_bios.c | ||
| intel_bios.h | ||
| intel_crt.c | ||
| intel_ddi.c | ||
| intel_display.c | ||
| intel_dp_mst.c | ||
| intel_dp.c | ||
| intel_drv.h | ||
| intel_dsi_cmd.c | ||
| intel_dsi_cmd.h | ||
| intel_dsi_panel_vbt.c | ||
| intel_dsi_pll.c | ||
| intel_dsi.c | ||
| intel_dsi.h | ||
| intel_dvo.c | ||
| intel_fbdev.c | ||
| intel_fifo_underrun.c | ||
| intel_frontbuffer.c | ||
| intel_hdmi.c | ||
| intel_i2c.c | ||
| intel_lrc.c | ||
| intel_lrc.h | ||
| intel_lvds.c | ||
| intel_modes.c | ||
| intel_opregion.c | ||
| intel_overlay.c | ||
| intel_panel.c | ||
| intel_pm.c | ||
| intel_psr.c | ||
| intel_renderstate_gen6.c | ||
| intel_renderstate_gen7.c | ||
| intel_renderstate_gen8.c | ||
| intel_renderstate_gen9.c | ||
| intel_renderstate.h | ||
| intel_ringbuffer.c | ||
| intel_ringbuffer.h | ||
| intel_runtime_pm.c | ||
| intel_sdvo_regs.h | ||
| intel_sdvo.c | ||
| intel_sideband.c | ||
| intel_sprite.c | ||
| intel_tv.c | ||
| intel_uncore.c | ||
| Kconfig | ||
| Makefile | ||