mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-21 11:44:01 +08:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
368 lines
9.1 KiB
C
368 lines
9.1 KiB
C
/* $Id: teles0.c,v 2.15.2.4 2004/01/13 23:48:39 keil Exp $
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*
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* low level stuff for Teles Memory IO isdn cards
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*
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* Author Karsten Keil
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* based on the teles driver from Jan den Ouden
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* Copyright by Karsten Keil <keil@isdn4linux.de>
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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* Thanks to Jan den Ouden
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* Fritz Elfert
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* Beat Doebeli
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*
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*/
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#include <linux/init.h>
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#include "hisax.h"
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#include "isdnl1.h"
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#include "isac.h"
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#include "hscx.h"
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extern const char *CardType[];
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const char *teles0_revision = "$Revision: 2.15.2.4 $";
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#define TELES_IOMEM_SIZE 0x400
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#define byteout(addr,val) outb(val,addr)
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#define bytein(addr) inb(addr)
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static inline u_char
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readisac(void __iomem *adr, u_char off)
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{
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return readb(adr + ((off & 1) ? 0x2ff : 0x100) + off);
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}
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static inline void
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writeisac(void __iomem *adr, u_char off, u_char data)
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{
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writeb(data, adr + ((off & 1) ? 0x2ff : 0x100) + off); mb();
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}
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static inline u_char
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readhscx(void __iomem *adr, int hscx, u_char off)
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{
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return readb(adr + (hscx ? 0x1c0 : 0x180) +
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((off & 1) ? 0x1ff : 0) + off);
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}
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static inline void
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writehscx(void __iomem *adr, int hscx, u_char off, u_char data)
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{
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writeb(data, adr + (hscx ? 0x1c0 : 0x180) +
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((off & 1) ? 0x1ff : 0) + off); mb();
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}
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static inline void
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read_fifo_isac(void __iomem *adr, u_char * data, int size)
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{
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register int i;
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register u_char __iomem *ad = adr + 0x100;
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for (i = 0; i < size; i++)
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data[i] = readb(ad);
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}
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static inline void
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write_fifo_isac(void __iomem *adr, u_char * data, int size)
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{
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register int i;
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register u_char __iomem *ad = adr + 0x100;
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for (i = 0; i < size; i++) {
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writeb(data[i], ad); mb();
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}
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}
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static inline void
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read_fifo_hscx(void __iomem *adr, int hscx, u_char * data, int size)
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{
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register int i;
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register u_char __iomem *ad = adr + (hscx ? 0x1c0 : 0x180);
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for (i = 0; i < size; i++)
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data[i] = readb(ad);
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}
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static inline void
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write_fifo_hscx(void __iomem *adr, int hscx, u_char * data, int size)
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{
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int i;
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register u_char __iomem *ad = adr + (hscx ? 0x1c0 : 0x180);
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for (i = 0; i < size; i++) {
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writeb(data[i], ad); mb();
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}
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}
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/* Interface functions */
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static u_char
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ReadISAC(struct IsdnCardState *cs, u_char offset)
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{
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return (readisac(cs->hw.teles0.membase, offset));
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}
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static void
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WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
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{
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writeisac(cs->hw.teles0.membase, offset, value);
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}
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static void
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ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
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{
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read_fifo_isac(cs->hw.teles0.membase, data, size);
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}
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static void
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WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
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{
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write_fifo_isac(cs->hw.teles0.membase, data, size);
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}
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static u_char
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ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
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{
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return (readhscx(cs->hw.teles0.membase, hscx, offset));
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}
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static void
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WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
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{
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writehscx(cs->hw.teles0.membase, hscx, offset, value);
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}
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/*
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* fast interrupt HSCX stuff goes here
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*/
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#define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
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#define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
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#define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
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#define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
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#include "hscx_irq.c"
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static irqreturn_t
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teles0_interrupt(int intno, void *dev_id, struct pt_regs *regs)
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{
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struct IsdnCardState *cs = dev_id;
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u_char val;
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u_long flags;
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int count = 0;
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spin_lock_irqsave(&cs->lock, flags);
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val = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA);
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Start_HSCX:
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if (val)
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hscx_int_main(cs, val);
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val = readisac(cs->hw.teles0.membase, ISAC_ISTA);
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Start_ISAC:
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if (val)
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isac_interrupt(cs, val);
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count++;
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val = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA);
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if (val && count < 5) {
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if (cs->debug & L1_DEB_HSCX)
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debugl1(cs, "HSCX IntStat after IntRoutine");
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goto Start_HSCX;
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}
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val = readisac(cs->hw.teles0.membase, ISAC_ISTA);
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if (val && count < 5) {
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "ISAC IntStat after IntRoutine");
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goto Start_ISAC;
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}
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writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0xFF);
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writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0xFF);
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writeisac(cs->hw.teles0.membase, ISAC_MASK, 0xFF);
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writeisac(cs->hw.teles0.membase, ISAC_MASK, 0x0);
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writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0x0);
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writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0x0);
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spin_unlock_irqrestore(&cs->lock, flags);
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return IRQ_HANDLED;
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}
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void
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release_io_teles0(struct IsdnCardState *cs)
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{
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if (cs->hw.teles0.cfg_reg)
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release_region(cs->hw.teles0.cfg_reg, 8);
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iounmap(cs->hw.teles0.membase);
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release_mem_region(cs->hw.teles0.phymem, TELES_IOMEM_SIZE);
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}
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static int
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reset_teles0(struct IsdnCardState *cs)
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{
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u_char cfval;
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if (cs->hw.teles0.cfg_reg) {
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switch (cs->irq) {
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case 2:
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case 9:
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cfval = 0x00;
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break;
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case 3:
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cfval = 0x02;
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break;
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case 4:
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cfval = 0x04;
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break;
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case 5:
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cfval = 0x06;
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break;
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case 10:
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cfval = 0x08;
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break;
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case 11:
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cfval = 0x0A;
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break;
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case 12:
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cfval = 0x0C;
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break;
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case 15:
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cfval = 0x0E;
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break;
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default:
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return(1);
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}
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cfval |= ((cs->hw.teles0.phymem >> 9) & 0xF0);
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byteout(cs->hw.teles0.cfg_reg + 4, cfval);
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HZDELAY(HZ / 10 + 1);
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byteout(cs->hw.teles0.cfg_reg + 4, cfval | 1);
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HZDELAY(HZ / 10 + 1);
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}
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writeb(0, cs->hw.teles0.membase + 0x80); mb();
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HZDELAY(HZ / 5 + 1);
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writeb(1, cs->hw.teles0.membase + 0x80); mb();
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HZDELAY(HZ / 5 + 1);
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return(0);
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}
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static int
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Teles_card_msg(struct IsdnCardState *cs, int mt, void *arg)
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{
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u_long flags;
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switch (mt) {
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case CARD_RESET:
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spin_lock_irqsave(&cs->lock, flags);
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reset_teles0(cs);
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spin_unlock_irqrestore(&cs->lock, flags);
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return(0);
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case CARD_RELEASE:
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release_io_teles0(cs);
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return(0);
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case CARD_INIT:
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spin_lock_irqsave(&cs->lock, flags);
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inithscxisac(cs, 3);
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spin_unlock_irqrestore(&cs->lock, flags);
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return(0);
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case CARD_TEST:
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return(0);
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}
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return(0);
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}
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int __init
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setup_teles0(struct IsdnCard *card)
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{
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u_char val;
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struct IsdnCardState *cs = card->cs;
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char tmp[64];
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strcpy(tmp, teles0_revision);
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printk(KERN_INFO "HiSax: Teles 8.0/16.0 driver Rev. %s\n", HiSax_getrev(tmp));
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if ((cs->typ != ISDN_CTYPE_16_0) && (cs->typ != ISDN_CTYPE_8_0))
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return (0);
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if (cs->typ == ISDN_CTYPE_16_0)
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cs->hw.teles0.cfg_reg = card->para[2];
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else /* 8.0 */
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cs->hw.teles0.cfg_reg = 0;
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if (card->para[1] < 0x10000) {
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card->para[1] <<= 4;
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printk(KERN_INFO
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"Teles0: membase configured DOSish, assuming 0x%lx\n",
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(unsigned long) card->para[1]);
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}
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cs->irq = card->para[0];
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if (cs->hw.teles0.cfg_reg) {
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if (!request_region(cs->hw.teles0.cfg_reg, 8, "teles cfg")) {
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printk(KERN_WARNING
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"HiSax: %s config port %x-%x already in use\n",
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CardType[card->typ],
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cs->hw.teles0.cfg_reg,
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cs->hw.teles0.cfg_reg + 8);
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return (0);
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}
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}
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if (cs->hw.teles0.cfg_reg) {
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if ((val = bytein(cs->hw.teles0.cfg_reg + 0)) != 0x51) {
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printk(KERN_WARNING "Teles0: 16.0 Byte at %x is %x\n",
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cs->hw.teles0.cfg_reg + 0, val);
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release_region(cs->hw.teles0.cfg_reg, 8);
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return (0);
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}
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if ((val = bytein(cs->hw.teles0.cfg_reg + 1)) != 0x93) {
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printk(KERN_WARNING "Teles0: 16.0 Byte at %x is %x\n",
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cs->hw.teles0.cfg_reg + 1, val);
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release_region(cs->hw.teles0.cfg_reg, 8);
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return (0);
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}
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val = bytein(cs->hw.teles0.cfg_reg + 2); /* 0x1e=without AB
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* 0x1f=with AB
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* 0x1c 16.3 ???
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*/
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if (val != 0x1e && val != 0x1f) {
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printk(KERN_WARNING "Teles0: 16.0 Byte at %x is %x\n",
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cs->hw.teles0.cfg_reg + 2, val);
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release_region(cs->hw.teles0.cfg_reg, 8);
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return (0);
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}
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}
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/* 16.0 and 8.0 designed for IOM1 */
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test_and_set_bit(HW_IOM1, &cs->HW_Flags);
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cs->hw.teles0.phymem = card->para[1];
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if (!request_mem_region(cs->hw.teles0.phymem, TELES_IOMEM_SIZE, "teles iomem")) {
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printk(KERN_WARNING
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"HiSax: %s memory region %lx-%lx already in use\n",
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CardType[card->typ],
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cs->hw.teles0.phymem,
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cs->hw.teles0.phymem + TELES_IOMEM_SIZE);
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if (cs->hw.teles0.cfg_reg)
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release_region(cs->hw.teles0.cfg_reg, 8);
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return (0);
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}
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cs->hw.teles0.membase = ioremap(cs->hw.teles0.phymem, TELES_IOMEM_SIZE);
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printk(KERN_INFO
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"HiSax: %s config irq:%d mem:%p cfg:0x%X\n",
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CardType[cs->typ], cs->irq,
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cs->hw.teles0.membase, cs->hw.teles0.cfg_reg);
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if (reset_teles0(cs)) {
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printk(KERN_WARNING "Teles0: wrong IRQ\n");
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release_io_teles0(cs);
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return (0);
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}
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setup_isac(cs);
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cs->readisac = &ReadISAC;
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cs->writeisac = &WriteISAC;
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cs->readisacfifo = &ReadISACfifo;
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cs->writeisacfifo = &WriteISACfifo;
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cs->BC_Read_Reg = &ReadHSCX;
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cs->BC_Write_Reg = &WriteHSCX;
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cs->BC_Send_Data = &hscx_fill_fifo;
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cs->cardmsg = &Teles_card_msg;
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cs->irq_func = &teles0_interrupt;
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ISACVersion(cs, "Teles0:");
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if (HscxVersion(cs, "Teles0:")) {
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printk(KERN_WARNING
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"Teles0: wrong HSCX versions check IO/MEM addresses\n");
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release_io_teles0(cs);
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return (0);
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}
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return (1);
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}
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