mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-21 11:44:01 +08:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
1184 lines
32 KiB
C
1184 lines
32 KiB
C
/* $Id: diva.c,v 1.33.2.6 2004/02/11 13:21:33 keil Exp $
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*
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* low level stuff for Eicon.Diehl Diva Family ISDN cards
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*
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* Author Karsten Keil
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* Copyright by Karsten Keil <keil@isdn4linux.de>
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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* For changes and modifications please read
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* Documentation/isdn/HiSax.cert
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*
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* Thanks to Eicon Technology for documents and information
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*
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*/
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#include <linux/init.h>
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#include <linux/config.h>
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#include "hisax.h"
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#include "isac.h"
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#include "hscx.h"
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#include "ipac.h"
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#include "ipacx.h"
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#include "isdnl1.h"
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#include <linux/pci.h>
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#include <linux/isapnp.h>
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extern const char *CardType[];
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const char *Diva_revision = "$Revision: 1.33.2.6 $";
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#define byteout(addr,val) outb(val,addr)
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#define bytein(addr) inb(addr)
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#define DIVA_HSCX_DATA 0
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#define DIVA_HSCX_ADR 4
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#define DIVA_ISA_ISAC_DATA 2
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#define DIVA_ISA_ISAC_ADR 6
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#define DIVA_ISA_CTRL 7
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#define DIVA_IPAC_ADR 0
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#define DIVA_IPAC_DATA 1
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#define DIVA_PCI_ISAC_DATA 8
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#define DIVA_PCI_ISAC_ADR 0xc
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#define DIVA_PCI_CTRL 0x10
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/* SUB Types */
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#define DIVA_ISA 1
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#define DIVA_PCI 2
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#define DIVA_IPAC_ISA 3
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#define DIVA_IPAC_PCI 4
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#define DIVA_IPACX_PCI 5
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/* CTRL (Read) */
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#define DIVA_IRQ_STAT 0x01
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#define DIVA_EEPROM_SDA 0x02
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/* CTRL (Write) */
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#define DIVA_IRQ_REQ 0x01
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#define DIVA_RESET 0x08
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#define DIVA_EEPROM_CLK 0x40
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#define DIVA_PCI_LED_A 0x10
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#define DIVA_PCI_LED_B 0x20
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#define DIVA_ISA_LED_A 0x20
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#define DIVA_ISA_LED_B 0x40
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#define DIVA_IRQ_CLR 0x80
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/* Siemens PITA */
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#define PITA_MISC_REG 0x1c
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#ifdef __BIG_ENDIAN
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#define PITA_PARA_SOFTRESET 0x00000001
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#define PITA_SER_SOFTRESET 0x00000002
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#define PITA_PARA_MPX_MODE 0x00000004
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#define PITA_INT0_ENABLE 0x00000200
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#else
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#define PITA_PARA_SOFTRESET 0x01000000
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#define PITA_SER_SOFTRESET 0x02000000
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#define PITA_PARA_MPX_MODE 0x04000000
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#define PITA_INT0_ENABLE 0x00020000
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#endif
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#define PITA_INT0_STATUS 0x02
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static inline u_char
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readreg(unsigned int ale, unsigned int adr, u_char off)
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{
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register u_char ret;
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byteout(ale, off);
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ret = bytein(adr);
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return (ret);
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}
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static inline void
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readfifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
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{
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byteout(ale, off);
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insb(adr, data, size);
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}
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static inline void
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writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)
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{
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byteout(ale, off);
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byteout(adr, data);
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}
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static inline void
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writefifo(unsigned int ale, unsigned int adr, u_char off, u_char *data, int size)
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{
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byteout(ale, off);
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outsb(adr, data, size);
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}
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static inline u_char
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memreadreg(unsigned long adr, u_char off)
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{
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return(*((unsigned char *)
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(((unsigned int *)adr) + off)));
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}
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static inline void
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memwritereg(unsigned long adr, u_char off, u_char data)
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{
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register u_char *p;
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p = (unsigned char *)(((unsigned int *)adr) + off);
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*p = data;
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}
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/* Interface functions */
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static u_char
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ReadISAC(struct IsdnCardState *cs, u_char offset)
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{
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return(readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset));
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}
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static void
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WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
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{
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writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset, value);
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}
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static void
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ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size)
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{
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readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size);
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}
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static void
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WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size)
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{
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writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size);
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}
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static u_char
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ReadISAC_IPAC(struct IsdnCardState *cs, u_char offset)
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{
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return (readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset+0x80));
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}
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static void
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WriteISAC_IPAC(struct IsdnCardState *cs, u_char offset, u_char value)
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{
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writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset|0x80, value);
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}
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static void
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ReadISACfifo_IPAC(struct IsdnCardState *cs, u_char * data, int size)
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{
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readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0x80, data, size);
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}
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static void
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WriteISACfifo_IPAC(struct IsdnCardState *cs, u_char * data, int size)
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{
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writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0x80, data, size);
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}
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static u_char
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ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
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{
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return(readreg(cs->hw.diva.hscx_adr,
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cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0)));
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}
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static void
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WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
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{
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writereg(cs->hw.diva.hscx_adr,
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cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0), value);
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}
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static u_char
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MemReadISAC_IPAC(struct IsdnCardState *cs, u_char offset)
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{
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return (memreadreg(cs->hw.diva.cfg_reg, offset+0x80));
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}
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static void
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MemWriteISAC_IPAC(struct IsdnCardState *cs, u_char offset, u_char value)
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{
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memwritereg(cs->hw.diva.cfg_reg, offset|0x80, value);
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}
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static void
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MemReadISACfifo_IPAC(struct IsdnCardState *cs, u_char * data, int size)
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{
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while(size--)
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*data++ = memreadreg(cs->hw.diva.cfg_reg, 0x80);
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}
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static void
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MemWriteISACfifo_IPAC(struct IsdnCardState *cs, u_char * data, int size)
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{
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while(size--)
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memwritereg(cs->hw.diva.cfg_reg, 0x80, *data++);
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}
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static u_char
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MemReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
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{
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return(memreadreg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0)));
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}
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static void
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MemWriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
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{
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memwritereg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0), value);
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}
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/* IO-Functions for IPACX type cards */
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static u_char
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MemReadISAC_IPACX(struct IsdnCardState *cs, u_char offset)
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{
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return (memreadreg(cs->hw.diva.cfg_reg, offset));
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}
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static void
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MemWriteISAC_IPACX(struct IsdnCardState *cs, u_char offset, u_char value)
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{
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memwritereg(cs->hw.diva.cfg_reg, offset, value);
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}
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static void
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MemReadISACfifo_IPACX(struct IsdnCardState *cs, u_char * data, int size)
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{
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while(size--)
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*data++ = memreadreg(cs->hw.diva.cfg_reg, 0);
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}
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static void
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MemWriteISACfifo_IPACX(struct IsdnCardState *cs, u_char * data, int size)
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{
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while(size--)
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memwritereg(cs->hw.diva.cfg_reg, 0, *data++);
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}
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static u_char
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MemReadHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset)
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{
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return(memreadreg(cs->hw.diva.cfg_reg, offset +
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(hscx ? IPACX_OFF_B2 : IPACX_OFF_B1)));
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}
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static void
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MemWriteHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
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{
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memwritereg(cs->hw.diva.cfg_reg, offset +
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(hscx ? IPACX_OFF_B2 : IPACX_OFF_B1), value);
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}
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/*
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* fast interrupt HSCX stuff goes here
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*/
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#define READHSCX(cs, nr, reg) readreg(cs->hw.diva.hscx_adr, \
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cs->hw.diva.hscx, reg + (nr ? 0x40 : 0))
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#define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.diva.hscx_adr, \
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cs->hw.diva.hscx, reg + (nr ? 0x40 : 0), data)
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#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.diva.hscx_adr, \
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cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
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#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.diva.hscx_adr, \
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cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
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#include "hscx_irq.c"
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static irqreturn_t
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diva_interrupt(int intno, void *dev_id, struct pt_regs *regs)
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{
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struct IsdnCardState *cs = dev_id;
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u_char val, sval;
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u_long flags;
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int cnt=5;
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spin_lock_irqsave(&cs->lock, flags);
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while (((sval = bytein(cs->hw.diva.ctrl)) & DIVA_IRQ_REQ) && cnt) {
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val = readreg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_ISTA + 0x40);
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if (val)
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hscx_int_main(cs, val);
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val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA);
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if (val)
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isac_interrupt(cs, val);
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cnt--;
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}
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if (!cnt)
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printk(KERN_WARNING "Diva: IRQ LOOP\n");
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writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0xFF);
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writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0xFF);
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writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0xFF);
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writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0x0);
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writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0x0);
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writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0x0);
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spin_unlock_irqrestore(&cs->lock, flags);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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diva_irq_ipac_isa(int intno, void *dev_id, struct pt_regs *regs)
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{
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struct IsdnCardState *cs = dev_id;
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u_char ista,val;
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u_long flags;
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int icnt=5;
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spin_lock_irqsave(&cs->lock, flags);
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ista = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA);
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Start_IPACISA:
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if (cs->debug & L1_DEB_IPAC)
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debugl1(cs, "IPAC ISTA %02X", ista);
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if (ista & 0x0f) {
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val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, HSCX_ISTA + 0x40);
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if (ista & 0x01)
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val |= 0x01;
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if (ista & 0x04)
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val |= 0x02;
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if (ista & 0x08)
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val |= 0x04;
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if (val)
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hscx_int_main(cs, val);
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}
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if (ista & 0x20) {
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val = 0xfe & readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA + 0x80);
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if (val) {
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isac_interrupt(cs, val);
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}
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}
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if (ista & 0x10) {
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val = 0x01;
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isac_interrupt(cs, val);
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}
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ista = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA);
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if ((ista & 0x3f) && icnt) {
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icnt--;
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goto Start_IPACISA;
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}
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if (!icnt)
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printk(KERN_WARNING "DIVA IPAC IRQ LOOP\n");
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writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xFF);
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writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xC0);
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spin_unlock_irqrestore(&cs->lock, flags);
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return IRQ_HANDLED;
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}
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static inline void
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MemwaitforCEC(struct IsdnCardState *cs, int hscx)
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{
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int to = 50;
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while ((MemReadHSCX(cs, hscx, HSCX_STAR) & 0x04) && to) {
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udelay(1);
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to--;
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}
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if (!to)
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printk(KERN_WARNING "HiSax: waitforCEC timeout\n");
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}
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static inline void
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MemwaitforXFW(struct IsdnCardState *cs, int hscx)
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{
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int to = 50;
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while ((!(MemReadHSCX(cs, hscx, HSCX_STAR) & 0x44) == 0x40) && to) {
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udelay(1);
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to--;
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}
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if (!to)
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printk(KERN_WARNING "HiSax: waitforXFW timeout\n");
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}
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static inline void
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MemWriteHSCXCMDR(struct IsdnCardState *cs, int hscx, u_char data)
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{
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MemwaitforCEC(cs, hscx);
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MemWriteHSCX(cs, hscx, HSCX_CMDR, data);
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}
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static void
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Memhscx_empty_fifo(struct BCState *bcs, int count)
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{
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u_char *ptr;
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struct IsdnCardState *cs = bcs->cs;
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int cnt;
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if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
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debugl1(cs, "hscx_empty_fifo");
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if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "hscx_empty_fifo: incoming packet too large");
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MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80);
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bcs->hw.hscx.rcvidx = 0;
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return;
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}
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ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
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cnt = count;
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while (cnt--)
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*ptr++ = memreadreg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0);
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MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80);
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ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
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bcs->hw.hscx.rcvidx += count;
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if (cs->debug & L1_DEB_HSCX_FIFO) {
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char *t = bcs->blog;
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t += sprintf(t, "hscx_empty_fifo %c cnt %d",
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bcs->hw.hscx.hscx ? 'B' : 'A', count);
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QuickHex(t, ptr, count);
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debugl1(cs, bcs->blog);
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}
|
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}
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|
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static void
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Memhscx_fill_fifo(struct BCState *bcs)
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{
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struct IsdnCardState *cs = bcs->cs;
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int more, count, cnt;
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int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags)? 64: 32;
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u_char *ptr,*p;
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if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
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debugl1(cs, "hscx_fill_fifo");
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|
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if (!bcs->tx_skb)
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return;
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if (bcs->tx_skb->len <= 0)
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return;
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|
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more = (bcs->mode == L1_MODE_TRANS) ? 1 : 0;
|
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if (bcs->tx_skb->len > fifo_size) {
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more = !0;
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count = fifo_size;
|
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} else
|
|
count = bcs->tx_skb->len;
|
|
cnt = count;
|
|
MemwaitforXFW(cs, bcs->hw.hscx.hscx);
|
|
p = ptr = bcs->tx_skb->data;
|
|
skb_pull(bcs->tx_skb, count);
|
|
bcs->tx_cnt -= count;
|
|
bcs->hw.hscx.count += count;
|
|
while(cnt--)
|
|
memwritereg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0,
|
|
*p++);
|
|
MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, more ? 0x8 : 0xa);
|
|
if (cs->debug & L1_DEB_HSCX_FIFO) {
|
|
char *t = bcs->blog;
|
|
|
|
t += sprintf(t, "hscx_fill_fifo %c cnt %d",
|
|
bcs->hw.hscx.hscx ? 'B' : 'A', count);
|
|
QuickHex(t, ptr, count);
|
|
debugl1(cs, bcs->blog);
|
|
}
|
|
}
|
|
|
|
static inline void
|
|
Memhscx_interrupt(struct IsdnCardState *cs, u_char val, u_char hscx)
|
|
{
|
|
u_char r;
|
|
struct BCState *bcs = cs->bcs + hscx;
|
|
struct sk_buff *skb;
|
|
int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags)? 64: 32;
|
|
int count;
|
|
|
|
if (!test_bit(BC_FLG_INIT, &bcs->Flag))
|
|
return;
|
|
|
|
if (val & 0x80) { /* RME */
|
|
r = MemReadHSCX(cs, hscx, HSCX_RSTA);
|
|
if ((r & 0xf0) != 0xa0) {
|
|
if (!(r & 0x80))
|
|
if (cs->debug & L1_DEB_WARN)
|
|
debugl1(cs, "HSCX invalid frame");
|
|
if ((r & 0x40) && bcs->mode)
|
|
if (cs->debug & L1_DEB_WARN)
|
|
debugl1(cs, "HSCX RDO mode=%d",
|
|
bcs->mode);
|
|
if (!(r & 0x20))
|
|
if (cs->debug & L1_DEB_WARN)
|
|
debugl1(cs, "HSCX CRC error");
|
|
MemWriteHSCXCMDR(cs, hscx, 0x80);
|
|
} else {
|
|
count = MemReadHSCX(cs, hscx, HSCX_RBCL) & (
|
|
test_bit(HW_IPAC, &cs->HW_Flags)? 0x3f: 0x1f);
|
|
if (count == 0)
|
|
count = fifo_size;
|
|
Memhscx_empty_fifo(bcs, count);
|
|
if ((count = bcs->hw.hscx.rcvidx - 1) > 0) {
|
|
if (cs->debug & L1_DEB_HSCX_FIFO)
|
|
debugl1(cs, "HX Frame %d", count);
|
|
if (!(skb = dev_alloc_skb(count)))
|
|
printk(KERN_WARNING "HSCX: receive out of memory\n");
|
|
else {
|
|
memcpy(skb_put(skb, count), bcs->hw.hscx.rcvbuf, count);
|
|
skb_queue_tail(&bcs->rqueue, skb);
|
|
}
|
|
}
|
|
}
|
|
bcs->hw.hscx.rcvidx = 0;
|
|
schedule_event(bcs, B_RCVBUFREADY);
|
|
}
|
|
if (val & 0x40) { /* RPF */
|
|
Memhscx_empty_fifo(bcs, fifo_size);
|
|
if (bcs->mode == L1_MODE_TRANS) {
|
|
/* receive audio data */
|
|
if (!(skb = dev_alloc_skb(fifo_size)))
|
|
printk(KERN_WARNING "HiSax: receive out of memory\n");
|
|
else {
|
|
memcpy(skb_put(skb, fifo_size), bcs->hw.hscx.rcvbuf, fifo_size);
|
|
skb_queue_tail(&bcs->rqueue, skb);
|
|
}
|
|
bcs->hw.hscx.rcvidx = 0;
|
|
schedule_event(bcs, B_RCVBUFREADY);
|
|
}
|
|
}
|
|
if (val & 0x10) { /* XPR */
|
|
if (bcs->tx_skb) {
|
|
if (bcs->tx_skb->len) {
|
|
Memhscx_fill_fifo(bcs);
|
|
return;
|
|
} else {
|
|
if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
|
|
(PACKET_NOACK != bcs->tx_skb->pkt_type)) {
|
|
u_long flags;
|
|
spin_lock_irqsave(&bcs->aclock, flags);
|
|
bcs->ackcnt += bcs->hw.hscx.count;
|
|
spin_unlock_irqrestore(&bcs->aclock, flags);
|
|
schedule_event(bcs, B_ACKPENDING);
|
|
}
|
|
dev_kfree_skb_irq(bcs->tx_skb);
|
|
bcs->hw.hscx.count = 0;
|
|
bcs->tx_skb = NULL;
|
|
}
|
|
}
|
|
if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
|
|
bcs->hw.hscx.count = 0;
|
|
test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
|
|
Memhscx_fill_fifo(bcs);
|
|
} else {
|
|
test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
|
|
schedule_event(bcs, B_XMTBUFREADY);
|
|
}
|
|
}
|
|
}
|
|
|
|
static inline void
|
|
Memhscx_int_main(struct IsdnCardState *cs, u_char val)
|
|
{
|
|
|
|
u_char exval;
|
|
struct BCState *bcs;
|
|
|
|
if (val & 0x01) { // EXB
|
|
bcs = cs->bcs + 1;
|
|
exval = MemReadHSCX(cs, 1, HSCX_EXIR);
|
|
if (exval & 0x40) {
|
|
if (bcs->mode == 1)
|
|
Memhscx_fill_fifo(bcs);
|
|
else {
|
|
/* Here we lost an TX interrupt, so
|
|
* restart transmitting the whole frame.
|
|
*/
|
|
if (bcs->tx_skb) {
|
|
skb_push(bcs->tx_skb, bcs->hw.hscx.count);
|
|
bcs->tx_cnt += bcs->hw.hscx.count;
|
|
bcs->hw.hscx.count = 0;
|
|
}
|
|
MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01);
|
|
if (cs->debug & L1_DEB_WARN)
|
|
debugl1(cs, "HSCX B EXIR %x Lost TX", exval);
|
|
}
|
|
} else if (cs->debug & L1_DEB_HSCX)
|
|
debugl1(cs, "HSCX B EXIR %x", exval);
|
|
}
|
|
if (val & 0xf8) {
|
|
if (cs->debug & L1_DEB_HSCX)
|
|
debugl1(cs, "HSCX B interrupt %x", val);
|
|
Memhscx_interrupt(cs, val, 1);
|
|
}
|
|
if (val & 0x02) { // EXA
|
|
bcs = cs->bcs;
|
|
exval = MemReadHSCX(cs, 0, HSCX_EXIR);
|
|
if (exval & 0x40) {
|
|
if (bcs->mode == L1_MODE_TRANS)
|
|
Memhscx_fill_fifo(bcs);
|
|
else {
|
|
/* Here we lost an TX interrupt, so
|
|
* restart transmitting the whole frame.
|
|
*/
|
|
if (bcs->tx_skb) {
|
|
skb_push(bcs->tx_skb, bcs->hw.hscx.count);
|
|
bcs->tx_cnt += bcs->hw.hscx.count;
|
|
bcs->hw.hscx.count = 0;
|
|
}
|
|
MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01);
|
|
if (cs->debug & L1_DEB_WARN)
|
|
debugl1(cs, "HSCX A EXIR %x Lost TX", exval);
|
|
}
|
|
} else if (cs->debug & L1_DEB_HSCX)
|
|
debugl1(cs, "HSCX A EXIR %x", exval);
|
|
}
|
|
if (val & 0x04) { // ICA
|
|
exval = MemReadHSCX(cs, 0, HSCX_ISTA);
|
|
if (cs->debug & L1_DEB_HSCX)
|
|
debugl1(cs, "HSCX A interrupt %x", exval);
|
|
Memhscx_interrupt(cs, exval, 0);
|
|
}
|
|
}
|
|
|
|
static irqreturn_t
|
|
diva_irq_ipac_pci(int intno, void *dev_id, struct pt_regs *regs)
|
|
{
|
|
struct IsdnCardState *cs = dev_id;
|
|
u_char ista,val;
|
|
int icnt=5;
|
|
u_char *cfg;
|
|
u_long flags;
|
|
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
cfg = (u_char *) cs->hw.diva.pci_cfg;
|
|
val = *cfg;
|
|
if (!(val & PITA_INT0_STATUS)) {
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
return IRQ_NONE; /* other shared IRQ */
|
|
}
|
|
*cfg = PITA_INT0_STATUS; /* Reset pending INT0 */
|
|
ista = memreadreg(cs->hw.diva.cfg_reg, IPAC_ISTA);
|
|
Start_IPACPCI:
|
|
if (cs->debug & L1_DEB_IPAC)
|
|
debugl1(cs, "IPAC ISTA %02X", ista);
|
|
if (ista & 0x0f) {
|
|
val = memreadreg(cs->hw.diva.cfg_reg, HSCX_ISTA + 0x40);
|
|
if (ista & 0x01)
|
|
val |= 0x01;
|
|
if (ista & 0x04)
|
|
val |= 0x02;
|
|
if (ista & 0x08)
|
|
val |= 0x04;
|
|
if (val)
|
|
Memhscx_int_main(cs, val);
|
|
}
|
|
if (ista & 0x20) {
|
|
val = 0xfe & memreadreg(cs->hw.diva.cfg_reg, ISAC_ISTA + 0x80);
|
|
if (val) {
|
|
isac_interrupt(cs, val);
|
|
}
|
|
}
|
|
if (ista & 0x10) {
|
|
val = 0x01;
|
|
isac_interrupt(cs, val);
|
|
}
|
|
ista = memreadreg(cs->hw.diva.cfg_reg, IPAC_ISTA);
|
|
if ((ista & 0x3f) && icnt) {
|
|
icnt--;
|
|
goto Start_IPACPCI;
|
|
}
|
|
if (!icnt)
|
|
printk(KERN_WARNING "DIVA IPAC PCI IRQ LOOP\n");
|
|
memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xFF);
|
|
memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xC0);
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t
|
|
diva_irq_ipacx_pci(int intno, void *dev_id, struct pt_regs *regs)
|
|
{
|
|
struct IsdnCardState *cs = dev_id;
|
|
u_char val;
|
|
u_char *cfg;
|
|
u_long flags;
|
|
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
cfg = (u_char *) cs->hw.diva.pci_cfg;
|
|
val = *cfg;
|
|
if (!(val &PITA_INT0_STATUS)) {
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
return IRQ_NONE; // other shared IRQ
|
|
}
|
|
interrupt_ipacx(cs); // handler for chip
|
|
*cfg = PITA_INT0_STATUS; // Reset PLX interrupt
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
void
|
|
release_io_diva(struct IsdnCardState *cs)
|
|
{
|
|
int bytecnt;
|
|
|
|
if ((cs->subtyp == DIVA_IPAC_PCI) ||
|
|
(cs->subtyp == DIVA_IPACX_PCI) ) {
|
|
u_int *cfg = (unsigned int *)cs->hw.diva.pci_cfg;
|
|
|
|
*cfg = 0; /* disable INT0/1 */
|
|
*cfg = 2; /* reset pending INT0 */
|
|
iounmap((void *)cs->hw.diva.cfg_reg);
|
|
iounmap((void *)cs->hw.diva.pci_cfg);
|
|
return;
|
|
} else if (cs->subtyp != DIVA_IPAC_ISA) {
|
|
del_timer(&cs->hw.diva.tl);
|
|
if (cs->hw.diva.cfg_reg)
|
|
byteout(cs->hw.diva.ctrl, 0); /* LED off, Reset */
|
|
}
|
|
if ((cs->subtyp == DIVA_ISA) || (cs->subtyp == DIVA_IPAC_ISA))
|
|
bytecnt = 8;
|
|
else
|
|
bytecnt = 32;
|
|
if (cs->hw.diva.cfg_reg) {
|
|
release_region(cs->hw.diva.cfg_reg, bytecnt);
|
|
}
|
|
}
|
|
|
|
static void
|
|
reset_diva(struct IsdnCardState *cs)
|
|
{
|
|
if (cs->subtyp == DIVA_IPAC_ISA) {
|
|
writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_POTA2, 0x20);
|
|
mdelay(10);
|
|
writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_POTA2, 0x00);
|
|
mdelay(10);
|
|
writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xc0);
|
|
} else if (cs->subtyp == DIVA_IPAC_PCI) {
|
|
unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg +
|
|
PITA_MISC_REG);
|
|
*ireg = PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE;
|
|
mdelay(10);
|
|
*ireg = PITA_PARA_MPX_MODE;
|
|
mdelay(10);
|
|
memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xc0);
|
|
} else if (cs->subtyp == DIVA_IPACX_PCI) {
|
|
unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg +
|
|
PITA_MISC_REG);
|
|
*ireg = PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE;
|
|
mdelay(10);
|
|
*ireg = PITA_PARA_MPX_MODE | PITA_SER_SOFTRESET;
|
|
mdelay(10);
|
|
MemWriteISAC_IPACX(cs, IPACX_MASK, 0xff); // Interrupts off
|
|
} else { /* DIVA 2.0 */
|
|
cs->hw.diva.ctrl_reg = 0; /* Reset On */
|
|
byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
|
|
mdelay(10);
|
|
cs->hw.diva.ctrl_reg |= DIVA_RESET; /* Reset Off */
|
|
byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
|
|
mdelay(10);
|
|
if (cs->subtyp == DIVA_ISA)
|
|
cs->hw.diva.ctrl_reg |= DIVA_ISA_LED_A;
|
|
else {
|
|
/* Workaround PCI9060 */
|
|
byteout(cs->hw.diva.pci_cfg + 0x69, 9);
|
|
cs->hw.diva.ctrl_reg |= DIVA_PCI_LED_A;
|
|
}
|
|
byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
|
|
}
|
|
}
|
|
|
|
#define DIVA_ASSIGN 1
|
|
|
|
static void
|
|
diva_led_handler(struct IsdnCardState *cs)
|
|
{
|
|
int blink = 0;
|
|
|
|
if ((cs->subtyp == DIVA_IPAC_ISA) ||
|
|
(cs->subtyp == DIVA_IPAC_PCI) ||
|
|
(cs->subtyp == DIVA_IPACX_PCI) )
|
|
return;
|
|
del_timer(&cs->hw.diva.tl);
|
|
if (cs->hw.diva.status & DIVA_ASSIGN)
|
|
cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ?
|
|
DIVA_ISA_LED_A : DIVA_PCI_LED_A;
|
|
else {
|
|
cs->hw.diva.ctrl_reg ^= (DIVA_ISA == cs->subtyp) ?
|
|
DIVA_ISA_LED_A : DIVA_PCI_LED_A;
|
|
blink = 250;
|
|
}
|
|
if (cs->hw.diva.status & 0xf000)
|
|
cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ?
|
|
DIVA_ISA_LED_B : DIVA_PCI_LED_B;
|
|
else if (cs->hw.diva.status & 0x0f00) {
|
|
cs->hw.diva.ctrl_reg ^= (DIVA_ISA == cs->subtyp) ?
|
|
DIVA_ISA_LED_B : DIVA_PCI_LED_B;
|
|
blink = 500;
|
|
} else
|
|
cs->hw.diva.ctrl_reg &= ~((DIVA_ISA == cs->subtyp) ?
|
|
DIVA_ISA_LED_B : DIVA_PCI_LED_B);
|
|
|
|
byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
|
|
if (blink) {
|
|
init_timer(&cs->hw.diva.tl);
|
|
cs->hw.diva.tl.expires = jiffies + ((blink * HZ) / 1000);
|
|
add_timer(&cs->hw.diva.tl);
|
|
}
|
|
}
|
|
|
|
static int
|
|
Diva_card_msg(struct IsdnCardState *cs, int mt, void *arg)
|
|
{
|
|
u_int *ireg;
|
|
u_long flags;
|
|
|
|
switch (mt) {
|
|
case CARD_RESET:
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
reset_diva(cs);
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
return(0);
|
|
case CARD_RELEASE:
|
|
release_io_diva(cs);
|
|
return(0);
|
|
case CARD_INIT:
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
reset_diva(cs);
|
|
if (cs->subtyp == DIVA_IPACX_PCI) {
|
|
ireg = (unsigned int *)cs->hw.diva.pci_cfg;
|
|
*ireg = PITA_INT0_ENABLE;
|
|
init_ipacx(cs, 3); // init chip and enable interrupts
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
return (0);
|
|
}
|
|
if (cs->subtyp == DIVA_IPAC_PCI) {
|
|
ireg = (unsigned int *)cs->hw.diva.pci_cfg;
|
|
*ireg = PITA_INT0_ENABLE;
|
|
}
|
|
inithscxisac(cs, 3);
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
return(0);
|
|
case CARD_TEST:
|
|
return(0);
|
|
case (MDL_REMOVE | REQUEST):
|
|
cs->hw.diva.status = 0;
|
|
break;
|
|
case (MDL_ASSIGN | REQUEST):
|
|
cs->hw.diva.status |= DIVA_ASSIGN;
|
|
break;
|
|
case MDL_INFO_SETUP:
|
|
if ((long)arg)
|
|
cs->hw.diva.status |= 0x0200;
|
|
else
|
|
cs->hw.diva.status |= 0x0100;
|
|
break;
|
|
case MDL_INFO_CONN:
|
|
if ((long)arg)
|
|
cs->hw.diva.status |= 0x2000;
|
|
else
|
|
cs->hw.diva.status |= 0x1000;
|
|
break;
|
|
case MDL_INFO_REL:
|
|
if ((long)arg) {
|
|
cs->hw.diva.status &= ~0x2000;
|
|
cs->hw.diva.status &= ~0x0200;
|
|
} else {
|
|
cs->hw.diva.status &= ~0x1000;
|
|
cs->hw.diva.status &= ~0x0100;
|
|
}
|
|
break;
|
|
}
|
|
if ((cs->subtyp != DIVA_IPAC_ISA) &&
|
|
(cs->subtyp != DIVA_IPAC_PCI) &&
|
|
(cs->subtyp != DIVA_IPACX_PCI)) {
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
diva_led_handler(cs);
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
}
|
|
return(0);
|
|
}
|
|
|
|
static struct pci_dev *dev_diva __initdata = NULL;
|
|
static struct pci_dev *dev_diva_u __initdata = NULL;
|
|
static struct pci_dev *dev_diva201 __initdata = NULL;
|
|
static struct pci_dev *dev_diva202 __initdata = NULL;
|
|
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#ifdef __ISAPNP__
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static struct isapnp_device_id diva_ids[] __initdata = {
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{ ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x51),
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ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x51),
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(unsigned long) "Diva picola" },
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{ ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x51),
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ISAPNP_VENDOR('E', 'I', 'C'), ISAPNP_FUNCTION(0x51),
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(unsigned long) "Diva picola" },
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{ ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x71),
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ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x71),
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(unsigned long) "Diva 2.0" },
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{ ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x71),
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ISAPNP_VENDOR('E', 'I', 'C'), ISAPNP_FUNCTION(0x71),
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(unsigned long) "Diva 2.0" },
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{ ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0xA1),
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ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0xA1),
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(unsigned long) "Diva 2.01" },
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{ ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0xA1),
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ISAPNP_VENDOR('E', 'I', 'C'), ISAPNP_FUNCTION(0xA1),
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(unsigned long) "Diva 2.01" },
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{ 0, }
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};
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static struct isapnp_device_id *ipid __initdata = &diva_ids[0];
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static struct pnp_card *pnp_c __devinitdata = NULL;
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#endif
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int __init
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setup_diva(struct IsdnCard *card)
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{
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int bytecnt = 8;
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u_char val;
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struct IsdnCardState *cs = card->cs;
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char tmp[64];
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strcpy(tmp, Diva_revision);
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printk(KERN_INFO "HiSax: Eicon.Diehl Diva driver Rev. %s\n", HiSax_getrev(tmp));
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if (cs->typ != ISDN_CTYPE_DIEHLDIVA)
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return(0);
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cs->hw.diva.status = 0;
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if (card->para[1]) {
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cs->hw.diva.ctrl_reg = 0;
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cs->hw.diva.cfg_reg = card->para[1];
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val = readreg(cs->hw.diva.cfg_reg + DIVA_IPAC_ADR,
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cs->hw.diva.cfg_reg + DIVA_IPAC_DATA, IPAC_ID);
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printk(KERN_INFO "Diva: IPAC version %x\n", val);
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if ((val == 1) || (val==2)) {
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cs->subtyp = DIVA_IPAC_ISA;
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cs->hw.diva.ctrl = 0;
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cs->hw.diva.isac = card->para[1] + DIVA_IPAC_DATA;
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cs->hw.diva.hscx = card->para[1] + DIVA_IPAC_DATA;
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cs->hw.diva.isac_adr = card->para[1] + DIVA_IPAC_ADR;
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cs->hw.diva.hscx_adr = card->para[1] + DIVA_IPAC_ADR;
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test_and_set_bit(HW_IPAC, &cs->HW_Flags);
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} else {
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cs->subtyp = DIVA_ISA;
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cs->hw.diva.ctrl = card->para[1] + DIVA_ISA_CTRL;
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cs->hw.diva.isac = card->para[1] + DIVA_ISA_ISAC_DATA;
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cs->hw.diva.hscx = card->para[1] + DIVA_HSCX_DATA;
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cs->hw.diva.isac_adr = card->para[1] + DIVA_ISA_ISAC_ADR;
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cs->hw.diva.hscx_adr = card->para[1] + DIVA_HSCX_ADR;
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}
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cs->irq = card->para[0];
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} else {
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#ifdef __ISAPNP__
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if (isapnp_present()) {
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struct pnp_dev *pnp_d;
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while(ipid->card_vendor) {
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if ((pnp_c = pnp_find_card(ipid->card_vendor,
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ipid->card_device, pnp_c))) {
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pnp_d = NULL;
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if ((pnp_d = pnp_find_dev(pnp_c,
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ipid->vendor, ipid->function, pnp_d))) {
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int err;
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printk(KERN_INFO "HiSax: %s detected\n",
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(char *)ipid->driver_data);
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pnp_disable_dev(pnp_d);
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err = pnp_activate_dev(pnp_d);
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if (err<0) {
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printk(KERN_WARNING "%s: pnp_activate_dev ret(%d)\n",
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__FUNCTION__, err);
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return(0);
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}
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card->para[1] = pnp_port_start(pnp_d, 0);
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card->para[0] = pnp_irq(pnp_d, 0);
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if (!card->para[0] || !card->para[1]) {
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printk(KERN_ERR "Diva PnP:some resources are missing %ld/%lx\n",
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card->para[0], card->para[1]);
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pnp_disable_dev(pnp_d);
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return(0);
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}
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cs->hw.diva.cfg_reg = card->para[1];
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cs->irq = card->para[0];
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if (ipid->function == ISAPNP_FUNCTION(0xA1)) {
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cs->subtyp = DIVA_IPAC_ISA;
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cs->hw.diva.ctrl = 0;
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cs->hw.diva.isac =
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card->para[1] + DIVA_IPAC_DATA;
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cs->hw.diva.hscx =
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card->para[1] + DIVA_IPAC_DATA;
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cs->hw.diva.isac_adr =
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card->para[1] + DIVA_IPAC_ADR;
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cs->hw.diva.hscx_adr =
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card->para[1] + DIVA_IPAC_ADR;
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test_and_set_bit(HW_IPAC, &cs->HW_Flags);
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} else {
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cs->subtyp = DIVA_ISA;
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cs->hw.diva.ctrl =
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card->para[1] + DIVA_ISA_CTRL;
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cs->hw.diva.isac =
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card->para[1] + DIVA_ISA_ISAC_DATA;
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cs->hw.diva.hscx =
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card->para[1] + DIVA_HSCX_DATA;
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cs->hw.diva.isac_adr =
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card->para[1] + DIVA_ISA_ISAC_ADR;
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cs->hw.diva.hscx_adr =
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card->para[1] + DIVA_HSCX_ADR;
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}
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goto ready;
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} else {
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printk(KERN_ERR "Diva PnP: PnP error card found, no device\n");
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return(0);
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}
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}
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ipid++;
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pnp_c=NULL;
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}
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if (!ipid->card_vendor) {
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printk(KERN_INFO "Diva PnP: no ISAPnP card found\n");
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}
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}
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#endif
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#ifdef CONFIG_PCI
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cs->subtyp = 0;
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if ((dev_diva = pci_find_device(PCI_VENDOR_ID_EICON,
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PCI_DEVICE_ID_EICON_DIVA20, dev_diva))) {
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if (pci_enable_device(dev_diva))
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return(0);
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cs->subtyp = DIVA_PCI;
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cs->irq = dev_diva->irq;
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cs->hw.diva.cfg_reg = pci_resource_start(dev_diva, 2);
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} else if ((dev_diva_u = pci_find_device(PCI_VENDOR_ID_EICON,
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PCI_DEVICE_ID_EICON_DIVA20_U, dev_diva_u))) {
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if (pci_enable_device(dev_diva_u))
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return(0);
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cs->subtyp = DIVA_PCI;
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cs->irq = dev_diva_u->irq;
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cs->hw.diva.cfg_reg = pci_resource_start(dev_diva_u, 2);
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} else if ((dev_diva201 = pci_find_device(PCI_VENDOR_ID_EICON,
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PCI_DEVICE_ID_EICON_DIVA201, dev_diva201))) {
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if (pci_enable_device(dev_diva201))
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return(0);
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cs->subtyp = DIVA_IPAC_PCI;
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cs->irq = dev_diva201->irq;
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cs->hw.diva.pci_cfg =
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(ulong) ioremap(pci_resource_start(dev_diva201, 0), 4096);
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cs->hw.diva.cfg_reg =
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(ulong) ioremap(pci_resource_start(dev_diva201, 1), 4096);
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} else if ((dev_diva202 = pci_find_device(PCI_VENDOR_ID_EICON,
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PCI_DEVICE_ID_EICON_DIVA202, dev_diva202))) {
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if (pci_enable_device(dev_diva202))
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return(0);
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cs->subtyp = DIVA_IPACX_PCI;
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cs->irq = dev_diva202->irq;
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cs->hw.diva.pci_cfg =
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(ulong) ioremap(pci_resource_start(dev_diva202, 0), 4096);
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cs->hw.diva.cfg_reg =
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(ulong) ioremap(pci_resource_start(dev_diva202, 1), 4096);
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} else {
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printk(KERN_WARNING "Diva: No PCI card found\n");
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return(0);
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}
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if (!cs->irq) {
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printk(KERN_WARNING "Diva: No IRQ for PCI card found\n");
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return(0);
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}
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if (!cs->hw.diva.cfg_reg) {
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printk(KERN_WARNING "Diva: No IO-Adr for PCI card found\n");
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return(0);
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}
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cs->irq_flags |= SA_SHIRQ;
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#else
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printk(KERN_WARNING "Diva: cfgreg 0 and NO_PCI_BIOS\n");
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printk(KERN_WARNING "Diva: unable to config DIVA PCI\n");
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return (0);
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#endif /* CONFIG_PCI */
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if ((cs->subtyp == DIVA_IPAC_PCI) ||
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(cs->subtyp == DIVA_IPACX_PCI) ) {
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cs->hw.diva.ctrl = 0;
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cs->hw.diva.isac = 0;
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cs->hw.diva.hscx = 0;
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cs->hw.diva.isac_adr = 0;
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cs->hw.diva.hscx_adr = 0;
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test_and_set_bit(HW_IPAC, &cs->HW_Flags);
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bytecnt = 0;
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} else {
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cs->hw.diva.ctrl = cs->hw.diva.cfg_reg + DIVA_PCI_CTRL;
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cs->hw.diva.isac = cs->hw.diva.cfg_reg + DIVA_PCI_ISAC_DATA;
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cs->hw.diva.hscx = cs->hw.diva.cfg_reg + DIVA_HSCX_DATA;
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cs->hw.diva.isac_adr = cs->hw.diva.cfg_reg + DIVA_PCI_ISAC_ADR;
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cs->hw.diva.hscx_adr = cs->hw.diva.cfg_reg + DIVA_HSCX_ADR;
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bytecnt = 32;
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}
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}
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ready:
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printk(KERN_INFO
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"Diva: %s card configured at %#lx IRQ %d\n",
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(cs->subtyp == DIVA_PCI) ? "PCI" :
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(cs->subtyp == DIVA_ISA) ? "ISA" :
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(cs->subtyp == DIVA_IPAC_ISA) ? "IPAC ISA" :
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(cs->subtyp == DIVA_IPAC_PCI) ? "IPAC PCI" : "IPACX PCI",
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cs->hw.diva.cfg_reg, cs->irq);
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if ((cs->subtyp == DIVA_IPAC_PCI) ||
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(cs->subtyp == DIVA_IPACX_PCI) ||
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(cs->subtyp == DIVA_PCI) )
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printk(KERN_INFO "Diva: %s space at %#lx\n",
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(cs->subtyp == DIVA_PCI) ? "PCI" :
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(cs->subtyp == DIVA_IPAC_PCI) ? "IPAC PCI" : "IPACX PCI",
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cs->hw.diva.pci_cfg);
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if ((cs->subtyp != DIVA_IPAC_PCI) &&
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(cs->subtyp != DIVA_IPACX_PCI) ) {
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if (!request_region(cs->hw.diva.cfg_reg, bytecnt, "diva isdn")) {
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printk(KERN_WARNING
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"HiSax: %s config port %lx-%lx already in use\n",
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CardType[card->typ],
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cs->hw.diva.cfg_reg,
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cs->hw.diva.cfg_reg + bytecnt);
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return (0);
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}
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}
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cs->BC_Read_Reg = &ReadHSCX;
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cs->BC_Write_Reg = &WriteHSCX;
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cs->BC_Send_Data = &hscx_fill_fifo;
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cs->cardmsg = &Diva_card_msg;
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setup_isac(cs);
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if (cs->subtyp == DIVA_IPAC_ISA) {
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cs->readisac = &ReadISAC_IPAC;
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cs->writeisac = &WriteISAC_IPAC;
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cs->readisacfifo = &ReadISACfifo_IPAC;
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cs->writeisacfifo = &WriteISACfifo_IPAC;
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cs->irq_func = &diva_irq_ipac_isa;
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val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ID);
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printk(KERN_INFO "Diva: IPAC version %x\n", val);
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} else if (cs->subtyp == DIVA_IPAC_PCI) {
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cs->readisac = &MemReadISAC_IPAC;
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cs->writeisac = &MemWriteISAC_IPAC;
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cs->readisacfifo = &MemReadISACfifo_IPAC;
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cs->writeisacfifo = &MemWriteISACfifo_IPAC;
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cs->BC_Read_Reg = &MemReadHSCX;
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cs->BC_Write_Reg = &MemWriteHSCX;
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cs->BC_Send_Data = &Memhscx_fill_fifo;
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cs->irq_func = &diva_irq_ipac_pci;
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val = memreadreg(cs->hw.diva.cfg_reg, IPAC_ID);
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printk(KERN_INFO "Diva: IPAC version %x\n", val);
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} else if (cs->subtyp == DIVA_IPACX_PCI) {
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cs->readisac = &MemReadISAC_IPACX;
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cs->writeisac = &MemWriteISAC_IPACX;
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cs->readisacfifo = &MemReadISACfifo_IPACX;
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cs->writeisacfifo = &MemWriteISACfifo_IPACX;
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cs->BC_Read_Reg = &MemReadHSCX_IPACX;
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cs->BC_Write_Reg = &MemWriteHSCX_IPACX;
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cs->BC_Send_Data = NULL; // function located in ipacx module
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cs->irq_func = &diva_irq_ipacx_pci;
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printk(KERN_INFO "Diva: IPACX Design Id: %x\n",
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MemReadISAC_IPACX(cs, IPACX_ID) &0x3F);
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} else { /* DIVA 2.0 */
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cs->hw.diva.tl.function = (void *) diva_led_handler;
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cs->hw.diva.tl.data = (long) cs;
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init_timer(&cs->hw.diva.tl);
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cs->readisac = &ReadISAC;
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cs->writeisac = &WriteISAC;
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cs->readisacfifo = &ReadISACfifo;
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cs->writeisacfifo = &WriteISACfifo;
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cs->irq_func = &diva_interrupt;
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ISACVersion(cs, "Diva:");
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if (HscxVersion(cs, "Diva:")) {
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printk(KERN_WARNING
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"Diva: wrong HSCX versions check IO address\n");
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release_io_diva(cs);
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return (0);
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}
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}
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return (1);
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}
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