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UFS host supplies the reference clock to UFS device and UFS device specification allows host to provide one of the 4 frequencies (19.2 MHz, 26 MHz, 38.4 MHz, 52 MHz) for reference clock. Host should set the device reference clock frequency setting in the device based on what frequency it is supplying to UFS device. Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Can Guo <cang@codeaurora.org> Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
80 lines
3.6 KiB
Plaintext
80 lines
3.6 KiB
Plaintext
* Universal Flash Storage (UFS) Host Controller
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UFSHC nodes are defined to describe on-chip UFS host controllers.
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Each UFS controller instance should have its own node.
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Required properties:
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- compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0", may
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also list one or more of the following:
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"qcom,msm8994-ufshc"
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"qcom,msm8996-ufshc"
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"qcom,ufshc"
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- interrupts : <interrupt mapping for UFS host controller IRQ>
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- reg : <registers mapping>
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Optional properties:
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- phys : phandle to UFS PHY node
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- phy-names : the string "ufsphy" when is found in a node, along
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with "phys" attribute, provides phandle to UFS PHY node
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- vdd-hba-supply : phandle to UFS host controller supply regulator node
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- vcc-supply : phandle to VCC supply regulator node
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- vccq-supply : phandle to VCCQ supply regulator node
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- vccq2-supply : phandle to VCCQ2 supply regulator node
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- vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V
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or 2.7-3.6V. This boolean property when set, specifies
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to use low voltage range of 1.7-1.95V. Note for external
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UFS cards this property is invalid and valid VCC range is
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always 2.7-3.6V.
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- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
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- vccq-max-microamp : specifies max. load that can be drawn from vccq supply
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- vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply
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- <name>-fixed-regulator : boolean property specifying that <name>-supply is a fixed regulator
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- clocks : List of phandle and clock specifier pairs
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- clock-names : List of clock input name strings sorted in the same
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order as the clocks property.
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"ref_clk" indicates reference clock frequency.
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UFS host supplies reference clock to UFS device and UFS device
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specification allows host to provide one of the 4 frequencies (19.2 MHz,
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26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is
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parsed and used to update the reference clock setting in device.
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Defaults to 26 MHz(as per specification) if not specified by host.
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- freq-table-hz : Array of <min max> operating frequencies stored in the same
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order as the clocks property. If this property is not
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defined or a value in the array is "0" then it is assumed
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that the frequency is set by the parent clock or a
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fixed rate clock source.
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-lanes-per-direction : number of lanes available per direction - either 1 or 2.
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Note that it is assume same number of lanes is used both
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directions at once. If not specified, default is 2 lanes per direction.
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- resets : reset node register
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- reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP.
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Note: If above properties are not defined it can be assumed that the supply
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regulators or clocks are always on.
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Example:
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ufshc@fc598000 {
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compatible = "jedec,ufs-1.1";
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reg = <0xfc598000 0x800>;
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interrupts = <0 28 0>;
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vdd-hba-supply = <&xxx_reg0>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&xxx_reg1>;
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vcc-supply-1p8;
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vccq-supply = <&xxx_reg2>;
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vccq2-supply = <&xxx_reg3>;
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vcc-max-microamp = 500000;
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vccq-max-microamp = 200000;
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vccq2-max-microamp = 200000;
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clocks = <&core 0>, <&ref 0>, <&phy 0>, <&iface 0>;
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clock-names = "core_clk", "ref_clk", "phy_clk", "iface_clk";
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freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>;
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resets = <&reset 0 1>;
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reset-names = "rst";
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phys = <&ufsphy1>;
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phy-names = "ufsphy";
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};
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