mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 20:53:53 +08:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
214 lines
5.5 KiB
C
214 lines
5.5 KiB
C
#ifndef __ASM_IO_APIC_H
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#define __ASM_IO_APIC_H
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#include <linux/config.h>
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#include <asm/types.h>
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#include <asm/mpspec.h>
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/*
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* Intel IO-APIC support for SMP and UP systems.
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*
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* Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
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*/
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#ifdef CONFIG_X86_IO_APIC
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#ifdef CONFIG_PCI_MSI
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static inline int use_pci_vector(void) {return 1;}
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static inline void disable_edge_ioapic_vector(unsigned int vector) { }
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static inline void mask_and_ack_level_ioapic_vector(unsigned int vector) { }
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static inline void end_edge_ioapic_vector (unsigned int vector) { }
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#define startup_level_ioapic startup_level_ioapic_vector
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#define shutdown_level_ioapic mask_IO_APIC_vector
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#define enable_level_ioapic unmask_IO_APIC_vector
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#define disable_level_ioapic mask_IO_APIC_vector
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#define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_vector
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#define end_level_ioapic end_level_ioapic_vector
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#define set_ioapic_affinity set_ioapic_affinity_vector
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#define startup_edge_ioapic startup_edge_ioapic_vector
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#define shutdown_edge_ioapic disable_edge_ioapic_vector
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#define enable_edge_ioapic unmask_IO_APIC_vector
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#define disable_edge_ioapic disable_edge_ioapic_vector
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#define ack_edge_ioapic ack_edge_ioapic_vector
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#define end_edge_ioapic end_edge_ioapic_vector
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#else
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static inline int use_pci_vector(void) {return 0;}
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static inline void disable_edge_ioapic_irq(unsigned int irq) { }
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static inline void mask_and_ack_level_ioapic_irq(unsigned int irq) { }
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static inline void end_edge_ioapic_irq (unsigned int irq) { }
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#define startup_level_ioapic startup_level_ioapic_irq
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#define shutdown_level_ioapic mask_IO_APIC_irq
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#define enable_level_ioapic unmask_IO_APIC_irq
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#define disable_level_ioapic mask_IO_APIC_irq
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#define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_irq
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#define end_level_ioapic end_level_ioapic_irq
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#define set_ioapic_affinity set_ioapic_affinity_irq
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#define startup_edge_ioapic startup_edge_ioapic_irq
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#define shutdown_edge_ioapic disable_edge_ioapic_irq
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#define enable_edge_ioapic unmask_IO_APIC_irq
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#define disable_edge_ioapic disable_edge_ioapic_irq
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#define ack_edge_ioapic ack_edge_ioapic_irq
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#define end_edge_ioapic end_edge_ioapic_irq
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#endif
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#define IO_APIC_BASE(idx) \
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((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \
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+ (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK)))
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/*
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* The structure of the IO-APIC:
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*/
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union IO_APIC_reg_00 {
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u32 raw;
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struct {
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u32 __reserved_2 : 14,
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LTS : 1,
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delivery_type : 1,
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__reserved_1 : 8,
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ID : 8;
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} __attribute__ ((packed)) bits;
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};
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union IO_APIC_reg_01 {
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u32 raw;
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struct {
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u32 version : 8,
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__reserved_2 : 7,
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PRQ : 1,
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entries : 8,
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__reserved_1 : 8;
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} __attribute__ ((packed)) bits;
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};
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union IO_APIC_reg_02 {
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u32 raw;
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struct {
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u32 __reserved_2 : 24,
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arbitration : 4,
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__reserved_1 : 4;
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} __attribute__ ((packed)) bits;
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};
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union IO_APIC_reg_03 {
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u32 raw;
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struct {
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u32 boot_DT : 1,
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__reserved_1 : 31;
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} __attribute__ ((packed)) bits;
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};
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/*
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* # of IO-APICs and # of IRQ routing registers
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*/
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extern int nr_ioapics;
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extern int nr_ioapic_registers[MAX_IO_APICS];
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enum ioapic_irq_destination_types {
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dest_Fixed = 0,
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dest_LowestPrio = 1,
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dest_SMI = 2,
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dest__reserved_1 = 3,
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dest_NMI = 4,
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dest_INIT = 5,
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dest__reserved_2 = 6,
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dest_ExtINT = 7
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};
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struct IO_APIC_route_entry {
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__u32 vector : 8,
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delivery_mode : 3, /* 000: FIXED
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* 001: lowest prio
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* 111: ExtINT
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*/
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dest_mode : 1, /* 0: physical, 1: logical */
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delivery_status : 1,
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polarity : 1,
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irr : 1,
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trigger : 1, /* 0: edge, 1: level */
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mask : 1, /* 0: enabled, 1: disabled */
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__reserved_2 : 15;
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union { struct { __u32
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__reserved_1 : 24,
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physical_dest : 4,
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__reserved_2 : 4;
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} physical;
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struct { __u32
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__reserved_1 : 24,
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logical_dest : 8;
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} logical;
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} dest;
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} __attribute__ ((packed));
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/*
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* MP-BIOS irq configuration table structures:
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*/
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/* I/O APIC entries */
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extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
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/* # of MP IRQ source entries */
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extern int mp_irq_entries;
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/* MP IRQ source entries */
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extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
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/* non-0 if default (table-less) MP configuration */
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extern int mpc_default_type;
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static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
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{
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*IO_APIC_BASE(apic) = reg;
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return *(IO_APIC_BASE(apic)+4);
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}
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static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
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{
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*IO_APIC_BASE(apic) = reg;
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*(IO_APIC_BASE(apic)+4) = value;
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}
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/*
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* Re-write a value: to be used for read-modify-write
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* cycles where the read already set up the index register.
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*
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* Older SiS APIC requires we rewrite the index regiser
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*/
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extern int sis_apic_bug;
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static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
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{
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if (sis_apic_bug)
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*IO_APIC_BASE(apic) = reg;
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*(IO_APIC_BASE(apic)+4) = value;
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}
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/* 1 if "noapic" boot option passed */
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extern int skip_ioapic_setup;
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/*
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* If we use the IO-APIC for IRQ routing, disable automatic
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* assignment of PCI IRQ's.
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*/
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#define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
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#ifdef CONFIG_ACPI_BOOT
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extern int io_apic_get_unique_id (int ioapic, int apic_id);
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extern int io_apic_get_version (int ioapic);
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extern int io_apic_get_redir_entries (int ioapic);
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extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low);
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#endif /*CONFIG_ACPI_BOOT*/
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extern int (*ioapic_renumber_irq)(int ioapic, int irq);
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#else /* !CONFIG_X86_IO_APIC */
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#define io_apic_assign_pci_irqs 0
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#endif
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extern int assign_irq_vector(int irq);
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#endif
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