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df863de19f
The system controller block in the Armada 375 has different register offsets for the system reset and other related functions. Therefore, this commit introduces the new "armada-375-system-controller" compatible string to identify the Armada 375 variant of the system controller. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
118 lines
3.2 KiB
C
118 lines
3.2 KiB
C
/*
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* System controller support for Armada 370, 375 and XP platforms.
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* The Armada 370, 375 and Armada XP SoCs have a range of
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* miscellaneous registers, that do not belong to a particular device,
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* but rather provide system-level features. This basic
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* system-controller driver provides a device tree binding for those
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* registers, and implements utility functions offering various
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* features related to those registers.
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*
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* For now, the feature set is limited to restarting the platform by a
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* soft-reset, but it might be extended in the future.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <linux/reboot.h>
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#include "common.h"
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static void __iomem *system_controller_base;
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struct mvebu_system_controller {
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u32 rstoutn_mask_offset;
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u32 system_soft_reset_offset;
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u32 rstoutn_mask_reset_out_en;
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u32 system_soft_reset;
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};
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static struct mvebu_system_controller *mvebu_sc;
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static const struct mvebu_system_controller armada_370_xp_system_controller = {
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.rstoutn_mask_offset = 0x60,
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.system_soft_reset_offset = 0x64,
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.rstoutn_mask_reset_out_en = 0x1,
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.system_soft_reset = 0x1,
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};
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static const struct mvebu_system_controller armada_375_system_controller = {
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.rstoutn_mask_offset = 0x54,
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.system_soft_reset_offset = 0x58,
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.rstoutn_mask_reset_out_en = 0x1,
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.system_soft_reset = 0x1,
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};
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static const struct mvebu_system_controller orion_system_controller = {
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.rstoutn_mask_offset = 0x108,
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.system_soft_reset_offset = 0x10c,
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.rstoutn_mask_reset_out_en = 0x4,
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.system_soft_reset = 0x1,
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};
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static const struct of_device_id of_system_controller_table[] = {
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{
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.compatible = "marvell,orion-system-controller",
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.data = (void *) &orion_system_controller,
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}, {
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.compatible = "marvell,armada-370-xp-system-controller",
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.data = (void *) &armada_370_xp_system_controller,
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}, {
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.compatible = "marvell,armada-375-system-controller",
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.data = (void *) &armada_375_system_controller,
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},
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{ /* end of list */ },
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};
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void mvebu_restart(enum reboot_mode mode, const char *cmd)
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{
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if (!system_controller_base) {
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pr_err("Cannot restart, system-controller not available: check the device tree\n");
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} else {
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/*
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* Enable soft reset to assert RSTOUTn.
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*/
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writel(mvebu_sc->rstoutn_mask_reset_out_en,
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system_controller_base +
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mvebu_sc->rstoutn_mask_offset);
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/*
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* Assert soft reset.
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*/
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writel(mvebu_sc->system_soft_reset,
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system_controller_base +
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mvebu_sc->system_soft_reset_offset);
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}
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while (1)
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;
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}
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static int __init mvebu_system_controller_init(void)
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{
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const struct of_device_id *match;
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struct device_node *np;
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np = of_find_matching_node_and_match(NULL, of_system_controller_table,
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&match);
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if (np) {
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system_controller_base = of_iomap(np, 0);
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mvebu_sc = (struct mvebu_system_controller *)match->data;
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of_node_put(np);
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}
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return 0;
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}
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arch_initcall(mvebu_system_controller_init);
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