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d452bca82d
irq_alloc_domain_generic_chips() can only be called once for an irqdomain. The sirfsoc init calls it twice and because the return value is not checked it does not notice the wreckage. The code works by chance because the first call already allocates two chips and therefor the second call to sirfsoc_alloc_gc() operates on the proper generic chip instance. Use a single call and setup the two chips in the obvious correct way. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Barry Song <baohua@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: Olof Johansson <olof@lixom.net> Link: http://lkml.kernel.org/r/20150706101543.470696950@linutronix.de
131 lines
3.5 KiB
C
131 lines
3.5 KiB
C
/*
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* interrupt controller support for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/irqdomain.h>
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#include <linux/syscore_ops.h>
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#include <asm/mach/irq.h>
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#include <asm/exception.h>
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#include "irqchip.h"
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#define SIRFSOC_INT_RISC_MASK0 0x0018
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#define SIRFSOC_INT_RISC_MASK1 0x001C
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#define SIRFSOC_INT_RISC_LEVEL0 0x0020
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#define SIRFSOC_INT_RISC_LEVEL1 0x0024
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#define SIRFSOC_INIT_IRQ_ID 0x0038
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#define SIRFSOC_INT_BASE_OFFSET 0x0004
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#define SIRFSOC_NUM_IRQS 64
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#define SIRFSOC_NUM_BANKS (SIRFSOC_NUM_IRQS / 32)
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static struct irq_domain *sirfsoc_irqdomain;
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static __init void sirfsoc_alloc_gc(void __iomem *base)
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{
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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unsigned int set = IRQ_LEVEL;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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int i;
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irq_alloc_domain_generic_chips(sirfsoc_irqdomain, 32, 1, "irq_sirfsoc",
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handle_level_irq, clr, set,
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IRQ_GC_INIT_MASK_CACHE);
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for (i = 0; i < SIRFSOC_NUM_BANKS; i++) {
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gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, i * 32);
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gc->reg_base = base + i * SIRFSOC_INT_BASE_OFFSET;
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
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}
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}
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static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
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{
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void __iomem *base = sirfsoc_irqdomain->host_data;
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u32 irqstat;
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irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
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handle_domain_irq(sirfsoc_irqdomain, irqstat & 0xff, regs);
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}
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static int __init sirfsoc_irq_init(struct device_node *np,
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struct device_node *parent)
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{
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void __iomem *base = of_iomap(np, 0);
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if (!base)
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panic("unable to map intc cpu registers\n");
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sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
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&irq_generic_chip_ops, base);
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sirfsoc_alloc_gc(base);
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writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
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writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);
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writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
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writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);
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set_handle_irq(sirfsoc_handle_irq);
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return 0;
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}
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IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);
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struct sirfsoc_irq_status {
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u32 mask0;
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u32 mask1;
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u32 level0;
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u32 level1;
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};
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static struct sirfsoc_irq_status sirfsoc_irq_st;
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static int sirfsoc_irq_suspend(void)
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{
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void __iomem *base = sirfsoc_irqdomain->host_data;
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sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
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sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
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sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
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sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
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return 0;
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}
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static void sirfsoc_irq_resume(void)
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{
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void __iomem *base = sirfsoc_irqdomain->host_data;
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writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
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writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
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writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
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writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
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}
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static struct syscore_ops sirfsoc_irq_syscore_ops = {
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.suspend = sirfsoc_irq_suspend,
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.resume = sirfsoc_irq_resume,
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};
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static int __init sirfsoc_irq_pm_init(void)
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{
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if (!sirfsoc_irqdomain)
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return 0;
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register_syscore_ops(&sirfsoc_irq_syscore_ops);
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return 0;
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}
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device_initcall(sirfsoc_irq_pm_init);
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