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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
355 lines
9.0 KiB
C
355 lines
9.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Broadcom BCM7120 style Level 2 interrupt controller driver
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*
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* Copyright (C) 2014 Broadcom Corporation
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/reboot.h>
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#include <linux/bitops.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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/* Register offset in the L2 interrupt controller */
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#define IRQEN 0x00
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#define IRQSTAT 0x04
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#define MAX_WORDS 4
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#define MAX_MAPPINGS (MAX_WORDS * 2)
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#define IRQS_PER_WORD 32
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struct bcm7120_l1_intc_data {
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struct bcm7120_l2_intc_data *b;
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u32 irq_map_mask[MAX_WORDS];
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};
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struct bcm7120_l2_intc_data {
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unsigned int n_words;
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void __iomem *map_base[MAX_MAPPINGS];
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void __iomem *pair_base[MAX_WORDS];
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int en_offset[MAX_WORDS];
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int stat_offset[MAX_WORDS];
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struct irq_domain *domain;
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bool can_wake;
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u32 irq_fwd_mask[MAX_WORDS];
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struct bcm7120_l1_intc_data *l1_data;
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int num_parent_irqs;
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const __be32 *map_mask_prop;
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};
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static void bcm7120_l2_intc_irq_handle(struct irq_desc *desc)
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{
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struct bcm7120_l1_intc_data *data = irq_desc_get_handler_data(desc);
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struct bcm7120_l2_intc_data *b = data->b;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int idx;
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chained_irq_enter(chip, desc);
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for (idx = 0; idx < b->n_words; idx++) {
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int base = idx * IRQS_PER_WORD;
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struct irq_chip_generic *gc =
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irq_get_domain_generic_chip(b->domain, base);
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unsigned long pending;
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int hwirq;
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irq_gc_lock(gc);
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pending = irq_reg_readl(gc, b->stat_offset[idx]) &
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gc->mask_cache &
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data->irq_map_mask[idx];
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irq_gc_unlock(gc);
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for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
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generic_handle_irq(irq_find_mapping(b->domain,
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base + hwirq));
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}
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}
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chained_irq_exit(chip, desc);
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}
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static void bcm7120_l2_intc_suspend(struct irq_chip_generic *gc)
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{
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struct bcm7120_l2_intc_data *b = gc->private;
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struct irq_chip_type *ct = gc->chip_types;
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irq_gc_lock(gc);
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if (b->can_wake)
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irq_reg_writel(gc, gc->mask_cache | gc->wake_active,
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ct->regs.mask);
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irq_gc_unlock(gc);
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}
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static void bcm7120_l2_intc_resume(struct irq_chip_generic *gc)
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{
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struct irq_chip_type *ct = gc->chip_types;
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/* Restore the saved mask */
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irq_gc_lock(gc);
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irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
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irq_gc_unlock(gc);
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}
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static int bcm7120_l2_intc_init_one(struct device_node *dn,
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struct bcm7120_l2_intc_data *data,
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int irq, u32 *valid_mask)
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{
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struct bcm7120_l1_intc_data *l1_data = &data->l1_data[irq];
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int parent_irq;
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unsigned int idx;
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parent_irq = irq_of_parse_and_map(dn, irq);
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if (!parent_irq) {
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pr_err("failed to map interrupt %d\n", irq);
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return -EINVAL;
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}
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/* For multiple parent IRQs with multiple words, this looks like:
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* <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
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*
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* We need to associate a given parent interrupt with its corresponding
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* map_mask in order to mask the status register with it because we
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* have the same handler being called for multiple parent interrupts.
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*
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* This is typically something needed on BCM7xxx (STB chips).
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*/
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for (idx = 0; idx < data->n_words; idx++) {
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if (data->map_mask_prop) {
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l1_data->irq_map_mask[idx] |=
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be32_to_cpup(data->map_mask_prop +
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irq * data->n_words + idx);
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} else {
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l1_data->irq_map_mask[idx] = 0xffffffff;
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}
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valid_mask[idx] |= l1_data->irq_map_mask[idx];
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}
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l1_data->b = data;
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irq_set_chained_handler_and_data(parent_irq,
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bcm7120_l2_intc_irq_handle, l1_data);
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return 0;
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}
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static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
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struct bcm7120_l2_intc_data *data)
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{
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int ret;
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data->map_base[0] = of_iomap(dn, 0);
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if (!data->map_base[0]) {
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pr_err("unable to map registers\n");
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return -ENOMEM;
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}
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data->pair_base[0] = data->map_base[0];
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data->en_offset[0] = IRQEN;
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data->stat_offset[0] = IRQSTAT;
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data->n_words = 1;
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ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
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data->irq_fwd_mask, data->n_words);
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if (ret != 0 && ret != -EINVAL) {
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/* property exists but has the wrong number of words */
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pr_err("invalid brcm,int-fwd-mask property\n");
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return -EINVAL;
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}
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data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
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if (!data->map_mask_prop ||
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(ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
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pr_err("invalid brcm,int-map-mask property\n");
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return -EINVAL;
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}
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return 0;
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}
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static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
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struct bcm7120_l2_intc_data *data)
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{
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unsigned int gc_idx;
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for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
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unsigned int map_idx = gc_idx * 2;
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void __iomem *en = of_iomap(dn, map_idx + 0);
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void __iomem *stat = of_iomap(dn, map_idx + 1);
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void __iomem *base = min(en, stat);
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data->map_base[map_idx + 0] = en;
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data->map_base[map_idx + 1] = stat;
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if (!base)
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break;
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data->pair_base[gc_idx] = base;
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data->en_offset[gc_idx] = en - base;
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data->stat_offset[gc_idx] = stat - base;
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}
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if (!gc_idx) {
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pr_err("unable to map registers\n");
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return -EINVAL;
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}
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data->n_words = gc_idx;
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return 0;
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}
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static int __init bcm7120_l2_intc_probe(struct device_node *dn,
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struct device_node *parent,
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int (*iomap_regs_fn)(struct device_node *,
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struct bcm7120_l2_intc_data *),
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const char *intc_name)
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{
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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struct bcm7120_l2_intc_data *data;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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int ret = 0;
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unsigned int idx, irq, flags;
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u32 valid_mask[MAX_WORDS] = { };
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->num_parent_irqs = of_irq_count(dn);
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if (data->num_parent_irqs <= 0) {
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pr_err("invalid number of parent interrupts\n");
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ret = -ENOMEM;
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goto out_unmap;
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}
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data->l1_data = kcalloc(data->num_parent_irqs, sizeof(*data->l1_data),
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GFP_KERNEL);
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if (!data->l1_data) {
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ret = -ENOMEM;
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goto out_free_l1_data;
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}
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ret = iomap_regs_fn(dn, data);
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if (ret < 0)
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goto out_free_l1_data;
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for (irq = 0; irq < data->num_parent_irqs; irq++) {
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ret = bcm7120_l2_intc_init_one(dn, data, irq, valid_mask);
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if (ret)
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goto out_free_l1_data;
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}
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data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
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&irq_generic_chip_ops, NULL);
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if (!data->domain) {
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ret = -ENOMEM;
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goto out_free_l1_data;
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}
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/* MIPS chips strapped for BE will automagically configure the
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* peripheral registers for CPU-native byte order.
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*/
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flags = IRQ_GC_INIT_MASK_CACHE;
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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flags |= IRQ_GC_BE_IO;
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ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
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dn->full_name, handle_level_irq, clr, 0, flags);
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if (ret) {
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pr_err("failed to allocate generic irq chip\n");
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goto out_free_domain;
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}
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if (of_property_read_bool(dn, "brcm,irq-can-wake"))
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data->can_wake = true;
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for (idx = 0; idx < data->n_words; idx++) {
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irq = idx * IRQS_PER_WORD;
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gc = irq_get_domain_generic_chip(data->domain, irq);
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gc->unused = 0xffffffff & ~valid_mask[idx];
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gc->private = data;
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ct = gc->chip_types;
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gc->reg_base = data->pair_base[idx];
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ct->regs.mask = data->en_offset[idx];
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/* gc->reg_base is defined and so is gc->writel */
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irq_reg_writel(gc, data->irq_fwd_mask[idx],
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data->en_offset[idx]);
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_ack = irq_gc_noop;
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gc->suspend = bcm7120_l2_intc_suspend;
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gc->resume = bcm7120_l2_intc_resume;
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/*
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* Initialize mask-cache, in case we need it for
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* saving/restoring fwd mask even w/o any child interrupts
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* installed
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*/
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gc->mask_cache = irq_reg_readl(gc, ct->regs.mask);
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if (data->can_wake) {
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/* This IRQ chip can wake the system, set all
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* relevant child interupts in wake_enabled mask
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*/
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gc->wake_enabled = 0xffffffff;
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gc->wake_enabled &= ~gc->unused;
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ct->chip.irq_set_wake = irq_gc_set_wake;
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}
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}
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pr_info("registered %s intc (%pOF, parent IRQ(s): %d)\n",
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intc_name, dn, data->num_parent_irqs);
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return 0;
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out_free_domain:
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irq_domain_remove(data->domain);
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out_free_l1_data:
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kfree(data->l1_data);
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out_unmap:
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for (idx = 0; idx < MAX_MAPPINGS; idx++) {
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if (data->map_base[idx])
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iounmap(data->map_base[idx]);
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}
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kfree(data);
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return ret;
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}
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static int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
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struct device_node *parent)
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{
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return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
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"BCM7120 L2");
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}
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static int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
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struct device_node *parent)
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{
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return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
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"BCM3380 L2");
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}
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IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc",
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bcm7120_l2_intc_probe_7120);
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IRQCHIP_DECLARE(bcm3380_l2_intc, "brcm,bcm3380-l2-intc",
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bcm7120_l2_intc_probe_3380);
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