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3b57de958e
This patch adds and modifies code to support multiple Multicast and Unicast Synopsys MAC filter configurations. The default configuration is defined to support legacy driver behavior, which is 64 Multicast bins. The Unicast filter code previously assumed all controllers support 32 or 16 Unicast addresses based on controller version number, but this has been corrected to support a default of 1 Unicast address. The filter configuration may be specified through the devicetree using a Synopsys specific device tree entry. This information was verified with Synopsys through Synopsys Support Case #8000684337 and shared with the maintainer. Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
146 lines
4.6 KiB
C
146 lines
4.6 KiB
C
/*******************************************************************************
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Header file for stmmac platform data
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Copyright (C) 2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#ifndef __STMMAC_PLATFORM_DATA
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#define __STMMAC_PLATFORM_DATA
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#include <linux/platform_device.h>
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#define STMMAC_RX_COE_NONE 0
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#define STMMAC_RX_COE_TYPE1 1
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#define STMMAC_RX_COE_TYPE2 2
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/* Define the macros for CSR clock range parameters to be passed by
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* platform code.
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* This could also be configured at run time using CPU freq framework. */
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/* MDC Clock Selection define*/
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#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
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#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
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#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
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#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
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#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
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#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
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/* The MDC clock could be set higher than the IEEE 802.3
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* specified frequency limit 0f 2.5 MHz, by programming a clock divider
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* of value different than the above defined values. The resultant MDIO
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* clock frequency of 12.5 MHz is applicable for the interfacing chips
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* supporting higher MDC clocks.
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* The MDC clock selection macros need to be defined for MDC clock rate
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* of 12.5 MHz, corresponding to the following selection.
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*/
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#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
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#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
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#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
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#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
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#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
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#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
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#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
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#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
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/* AXI DMA Burst length supported */
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#define DMA_AXI_BLEN_4 (1 << 1)
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#define DMA_AXI_BLEN_8 (1 << 2)
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#define DMA_AXI_BLEN_16 (1 << 3)
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#define DMA_AXI_BLEN_32 (1 << 4)
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#define DMA_AXI_BLEN_64 (1 << 5)
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#define DMA_AXI_BLEN_128 (1 << 6)
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#define DMA_AXI_BLEN_256 (1 << 7)
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#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
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| DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
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| DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
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/* Platfrom data for platform device structure's platform_data field */
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struct stmmac_mdio_bus_data {
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int (*phy_reset)(void *priv);
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unsigned int phy_mask;
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int *irqs;
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int probed_phy_irq;
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#ifdef CONFIG_OF
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int reset_gpio, active_low;
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u32 delays[3];
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#endif
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};
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struct stmmac_dma_cfg {
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int pbl;
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int fixed_burst;
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int mixed_burst;
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int burst_len;
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};
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struct plat_stmmacenet_data {
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char *phy_bus_name;
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int bus_id;
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int phy_addr;
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int interface;
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struct stmmac_mdio_bus_data *mdio_bus_data;
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struct stmmac_dma_cfg *dma_cfg;
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int clk_csr;
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int has_gmac;
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int enh_desc;
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int tx_coe;
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int rx_coe;
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int bugged_jumbo;
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int pmt;
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int force_sf_dma_mode;
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int force_thresh_dma_mode;
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int riwt_off;
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int max_speed;
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int maxmtu;
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int multicast_filter_bins;
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int unicast_filter_entries;
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void (*fix_mac_speed)(void *priv, unsigned int speed);
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void (*bus_setup)(void __iomem *ioaddr);
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void *(*setup)(struct platform_device *pdev);
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void (*free)(struct platform_device *pdev, void *priv);
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int (*init)(struct platform_device *pdev, void *priv);
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void (*exit)(struct platform_device *pdev, void *priv);
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void *custom_cfg;
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void *custom_data;
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void *bsp_priv;
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};
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/* of_data for SoC glue layer device tree bindings */
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struct stmmac_of_data {
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int has_gmac;
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int enh_desc;
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int tx_coe;
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int rx_coe;
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int bugged_jumbo;
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int pmt;
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int riwt_off;
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void (*fix_mac_speed)(void *priv, unsigned int speed);
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void (*bus_setup)(void __iomem *ioaddr);
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void *(*setup)(struct platform_device *pdev);
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void (*free)(struct platform_device *pdev, void *priv);
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int (*init)(struct platform_device *pdev, void *priv);
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void (*exit)(struct platform_device *pdev, void *priv);
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};
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#endif
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