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4749c02b8d
On Marvell EBU platforms, when doing suspend/resume, the SDRAM window configuration must be saved on suspend, and restored on resume. However, it needs to be restored on resume *before* re-entering the kernel, because the SDRAM window configuration defines the layout of the memory. For this reason, it cannot simply be done in the ->suspend() and ->resume() hooks of the mvebu-mbus driver. Instead, it needs to be restored by the bootloader "boot info" mechanism used when resuming. This mechanism allows the kernel to define a list of (address, value) pairs when suspending, that the bootloader will restore on resume before jumping back into the kernel. This commit therefore adds a new function to the mvebu-mbus driver, called mvebu_mbus_save_cpu_target(), which will be called by the platform code to make the mvebu-mbus driver save the SDRAM window configuration in a way that can be understood by the bootloader "boot info" mechanism. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1416585613-2113-8-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
80 lines
2.1 KiB
C
80 lines
2.1 KiB
C
/*
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* Marvell MBUS common definitions.
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*
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* Copyright (C) 2008 Marvell Semiconductor
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __LINUX_MBUS_H
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#define __LINUX_MBUS_H
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struct resource;
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struct mbus_dram_target_info
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{
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/*
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* The 4-bit MBUS target ID of the DRAM controller.
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*/
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u8 mbus_dram_target_id;
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/*
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* The base address, size, and MBUS attribute ID for each
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* of the possible DRAM chip selects. Peripherals are
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* required to support at least 4 decode windows.
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*/
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int num_cs;
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struct mbus_dram_window {
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u8 cs_index;
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u8 mbus_attr;
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u32 base;
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u32 size;
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} cs[4];
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};
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/* Flags for PCI/PCIe address decoding regions */
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#define MVEBU_MBUS_PCI_IO 0x1
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#define MVEBU_MBUS_PCI_MEM 0x2
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#define MVEBU_MBUS_PCI_WA 0x3
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/*
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* Magic value that explicits that we don't need a remapping-capable
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* address decoding window.
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*/
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#define MVEBU_MBUS_NO_REMAP (0xffffffff)
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/* Maximum size of a mbus window name */
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#define MVEBU_MBUS_MAX_WINNAME_SZ 32
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/*
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* The Marvell mbus is to be found only on SOCs from the Orion family
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* at the moment. Provide a dummy stub for other architectures.
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*/
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#ifdef CONFIG_PLAT_ORION
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extern const struct mbus_dram_target_info *mv_mbus_dram_info(void);
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#else
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static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
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{
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return NULL;
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}
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#endif
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int mvebu_mbus_save_cpu_target(u32 *store_addr);
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void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
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void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
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int mvebu_mbus_add_window_remap_by_id(unsigned int target,
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unsigned int attribute,
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phys_addr_t base, size_t size,
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phys_addr_t remap);
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int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
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phys_addr_t base, size_t size);
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int mvebu_mbus_del_window(phys_addr_t base, size_t size);
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int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
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size_t mbus_size, phys_addr_t sdram_phys_base,
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size_t sdram_size);
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int mvebu_mbus_dt_init(bool is_coherent);
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#endif /* __LINUX_MBUS_H */
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