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https://github.com/edk2-porting/linux-next.git
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d33fb1b9f0
UART3 clock rate is doubled in previous commit. This error is not detected until recently a mezzanine board which makes real use of uart3 port (through LS connector of 96boards) was setup and tested on hi3660-hikey960 board. This patch changes clock source rate of clk_factor_uart3 to 100000000. Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com> Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
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| .. | ||
| clk-hi3519.c | ||
| clk-hi3620.c | ||
| clk-hi3660.c | ||
| clk-hi6220-stub.c | ||
| clk-hi6220.c | ||
| clk-hip04.c | ||
| clk-hix5hd2.c | ||
| clk.c | ||
| clk.h | ||
| clkdivider-hi6220.c | ||
| clkgate-separated.c | ||
| crg-hi3516cv300.c | ||
| crg-hi3798cv200.c | ||
| crg.h | ||
| Kconfig | ||
| Makefile | ||
| reset.c | ||
| reset.h | ||