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The Allwinner A10 compatibles were following a slightly different compatible patterns than the rest of the SoCs for historical reasons. Add compatibles matching the other pattern to the clock driver for consistency, and keep the older one for backward compatibility. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
135 lines
4.9 KiB
Plaintext
135 lines
4.9 KiB
Plaintext
Device Tree Clock bindings for arch-sunxi
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
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"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
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"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
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"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
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"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
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"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
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"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
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"allwinner,sun4i-a10-axi-clk" - for the AXI clock
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"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
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"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
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"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
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"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
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"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
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"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
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"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
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"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
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"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
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"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
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"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
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"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
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"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
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"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
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"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
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"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
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"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
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"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
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"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
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"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
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"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
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"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
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"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
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"allwinner,sun7i-a20-out-clk" - for the external output clocks
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"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
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"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
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"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
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Required properties for all clocks:
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- reg : shall be the control register address for the clock.
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- clocks : shall be the input parent clock(s) phandle for the clock. For
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multiplexed clocks, the list order must match the hardware
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programming order.
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- #clock-cells : from common clock binding; shall be set to 0 except for
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"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
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"allwinner,sun4i-pll6-clk" where it shall be set to 1
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- clock-output-names : shall be the corresponding names of the outputs.
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If the clock module only has one output, the name shall be the
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module name.
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And "allwinner,*-usb-clk" clocks also require:
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- reset-cells : shall be set to 1
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For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
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dummy clocks at 25 MHz and 125 MHz, respectively. See example.
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Clock consumers should specify the desired clocks they use with a
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"clocks" phandle cell. Consumers that are using a gated clock should
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provide an additional ID in their clock property. This ID is the
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offset of the bit controlling this particular gate in the register.
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For example:
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osc24M: clk@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-osc-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&osc24M_fixed>;
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clock-output-names = "osc24M";
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};
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pll1: clk@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll1";
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};
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pll5: clk@01c20020 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-pll5-clk";
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reg = <0x01c20020 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll5_ddr", "pll5_other";
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};
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-cpu-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>;
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clock-output-names = "cpu";
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc0";
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};
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mii_phy_tx_clk: clk@2 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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clock-output-names = "mii_phy_tx";
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};
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gmac_int_tx_clk: clk@3 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "gmac_int_tx";
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};
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gmac_clk: clk@01c20164 {
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#clock-cells = <0>;
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compatible = "allwinner,sun7i-a20-gmac-clk";
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reg = <0x01c20164 0x4>;
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/*
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* The first clock must be fixed at 25MHz;
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* the second clock must be fixed at 125MHz
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*/
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clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
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clock-output-names = "gmac";
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};
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