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https://github.com/edk2-porting/linux-next.git
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65f6ae66a6
Because of the encoding of the "Multiple Message Capable" and "Multiple Message Enable" fields, a device can only advertise that it's capable of a power-of-two number of vectors, and the OS can only enable a power-of-two number. For example, a device that's limited internally to using 18 vectors would have to advertise that it's capable of 32. The 14 extra vectors consume vector numbers and IRQ descriptors even though the device can't actually use them. This fix introduces a 'msi_desc::nvec_used' field to address this issue. When non-zero, it is the actual number of MSIs the device will send, as requested by the device driver. This value should be used by architectures to set up and tear down only as many interrupt resources as the device will actually use. Note, although the existing 'msi_desc::multiple' field might seem redundant, in fact it is not. The number of MSIs advertised need not be the smallest power-of-two larger than the number of MSIs the device will send. Thus, it is not always possible to derive the former from the latter, so we need to keep them both to handle this case. [bhelgaas: changelog, rename to "nvec_used"] Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
1055 lines
26 KiB
C
1055 lines
26 KiB
C
/*
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* File: msi.c
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* Purpose: PCI Message Signaled Interrupt (MSI)
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*
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* Copyright (C) 2003-2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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#include <linux/err.h>
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#include <linux/mm.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/export.h>
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#include <linux/ioport.h>
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#include <linux/pci.h>
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#include <linux/proc_fs.h>
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#include <linux/msi.h>
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#include <linux/smp.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "pci.h"
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static int pci_msi_enable = 1;
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#define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
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/* Arch hooks */
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#ifndef arch_msi_check_device
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int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
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{
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return 0;
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}
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#endif
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#ifndef arch_setup_msi_irqs
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# define arch_setup_msi_irqs default_setup_msi_irqs
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# define HAVE_DEFAULT_MSI_SETUP_IRQS
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#endif
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#ifdef HAVE_DEFAULT_MSI_SETUP_IRQS
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int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
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{
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struct msi_desc *entry;
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int ret;
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/*
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* If an architecture wants to support multiple MSI, it needs to
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* override arch_setup_msi_irqs()
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*/
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if (type == PCI_CAP_ID_MSI && nvec > 1)
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return 1;
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list_for_each_entry(entry, &dev->msi_list, list) {
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ret = arch_setup_msi_irq(dev, entry);
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if (ret < 0)
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return ret;
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if (ret > 0)
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return -ENOSPC;
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}
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return 0;
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}
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#endif
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#ifndef arch_teardown_msi_irqs
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# define arch_teardown_msi_irqs default_teardown_msi_irqs
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# define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
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#endif
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#ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS
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void default_teardown_msi_irqs(struct pci_dev *dev)
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{
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struct msi_desc *entry;
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list_for_each_entry(entry, &dev->msi_list, list) {
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int i, nvec;
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if (entry->irq == 0)
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continue;
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if (entry->nvec_used)
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nvec = entry->nvec_used;
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else
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nvec = 1 << entry->msi_attrib.multiple;
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for (i = 0; i < nvec; i++)
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arch_teardown_msi_irq(entry->irq + i);
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}
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}
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#endif
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#ifndef arch_restore_msi_irqs
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# define arch_restore_msi_irqs default_restore_msi_irqs
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# define HAVE_DEFAULT_MSI_RESTORE_IRQS
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#endif
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#ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS
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void default_restore_msi_irqs(struct pci_dev *dev, int irq)
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{
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struct msi_desc *entry;
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entry = NULL;
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if (dev->msix_enabled) {
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list_for_each_entry(entry, &dev->msi_list, list) {
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if (irq == entry->irq)
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break;
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}
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} else if (dev->msi_enabled) {
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entry = irq_get_msi_desc(irq);
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}
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if (entry)
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write_msi_msg(irq, &entry->msg);
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}
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#endif
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static void msi_set_enable(struct pci_dev *dev, int enable)
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{
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u16 control;
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
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control &= ~PCI_MSI_FLAGS_ENABLE;
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if (enable)
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control |= PCI_MSI_FLAGS_ENABLE;
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pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
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}
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static void msix_set_enable(struct pci_dev *dev, int enable)
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{
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u16 control;
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pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
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control &= ~PCI_MSIX_FLAGS_ENABLE;
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if (enable)
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control |= PCI_MSIX_FLAGS_ENABLE;
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pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
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}
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static inline __attribute_const__ u32 msi_mask(unsigned x)
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{
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/* Don't shift by >= width of type */
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if (x >= 5)
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return 0xffffffff;
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return (1 << (1 << x)) - 1;
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}
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static inline __attribute_const__ u32 msi_capable_mask(u16 control)
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{
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return msi_mask((control >> 1) & 7);
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}
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static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
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{
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return msi_mask((control >> 4) & 7);
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}
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/*
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* PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
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* mask all MSI interrupts by clearing the MSI enable bit does not work
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* reliably as devices without an INTx disable bit will then generate a
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* level IRQ which will never be cleared.
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*/
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static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
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{
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u32 mask_bits = desc->masked;
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if (!desc->msi_attrib.maskbit)
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return 0;
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mask_bits &= ~mask;
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mask_bits |= flag;
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pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
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return mask_bits;
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}
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static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
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{
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desc->masked = __msi_mask_irq(desc, mask, flag);
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}
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/*
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* This internal function does not flush PCI writes to the device.
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* All users must ensure that they read from the device before either
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* assuming that the device state is up to date, or returning out of this
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* file. This saves a few milliseconds when initialising devices with lots
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* of MSI-X interrupts.
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*/
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static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
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{
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u32 mask_bits = desc->masked;
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unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
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PCI_MSIX_ENTRY_VECTOR_CTRL;
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mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
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if (flag)
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mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
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writel(mask_bits, desc->mask_base + offset);
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return mask_bits;
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}
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static void msix_mask_irq(struct msi_desc *desc, u32 flag)
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{
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desc->masked = __msix_mask_irq(desc, flag);
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}
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#ifdef CONFIG_GENERIC_HARDIRQS
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static void msi_set_mask_bit(struct irq_data *data, u32 flag)
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{
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struct msi_desc *desc = irq_data_get_msi(data);
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if (desc->msi_attrib.is_msix) {
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msix_mask_irq(desc, flag);
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readl(desc->mask_base); /* Flush write to device */
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} else {
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unsigned offset = data->irq - desc->dev->irq;
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msi_mask_irq(desc, 1 << offset, flag << offset);
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}
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}
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void mask_msi_irq(struct irq_data *data)
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{
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msi_set_mask_bit(data, 1);
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}
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void unmask_msi_irq(struct irq_data *data)
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{
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msi_set_mask_bit(data, 0);
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}
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#endif /* CONFIG_GENERIC_HARDIRQS */
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void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
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{
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BUG_ON(entry->dev->current_state != PCI_D0);
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if (entry->msi_attrib.is_msix) {
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void __iomem *base = entry->mask_base +
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entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
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msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
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msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
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msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
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} else {
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struct pci_dev *dev = entry->dev;
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int pos = dev->msi_cap;
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u16 data;
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pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
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&msg->address_lo);
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if (entry->msi_attrib.is_64) {
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pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
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&msg->address_hi);
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pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
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} else {
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msg->address_hi = 0;
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pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
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}
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msg->data = data;
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}
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}
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void read_msi_msg(unsigned int irq, struct msi_msg *msg)
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{
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struct msi_desc *entry = irq_get_msi_desc(irq);
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__read_msi_msg(entry, msg);
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}
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void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
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{
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/* Assert that the cache is valid, assuming that
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* valid messages are not all-zeroes. */
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BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
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entry->msg.data));
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*msg = entry->msg;
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}
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void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
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{
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struct msi_desc *entry = irq_get_msi_desc(irq);
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__get_cached_msi_msg(entry, msg);
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}
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void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
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{
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if (entry->dev->current_state != PCI_D0) {
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/* Don't touch the hardware now */
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} else if (entry->msi_attrib.is_msix) {
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void __iomem *base;
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base = entry->mask_base +
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entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
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writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
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writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
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writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
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} else {
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struct pci_dev *dev = entry->dev;
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int pos = dev->msi_cap;
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u16 msgctl;
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pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
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msgctl &= ~PCI_MSI_FLAGS_QSIZE;
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msgctl |= entry->msi_attrib.multiple << 4;
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pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
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pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
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msg->address_lo);
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if (entry->msi_attrib.is_64) {
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pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
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msg->address_hi);
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pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
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msg->data);
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} else {
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pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
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msg->data);
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}
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}
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entry->msg = *msg;
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}
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void write_msi_msg(unsigned int irq, struct msi_msg *msg)
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{
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struct msi_desc *entry = irq_get_msi_desc(irq);
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__write_msi_msg(entry, msg);
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}
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static void free_msi_irqs(struct pci_dev *dev)
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{
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struct msi_desc *entry, *tmp;
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list_for_each_entry(entry, &dev->msi_list, list) {
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int i, nvec;
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if (!entry->irq)
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continue;
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if (entry->nvec_used)
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nvec = entry->nvec_used;
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else
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nvec = 1 << entry->msi_attrib.multiple;
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#ifdef CONFIG_GENERIC_HARDIRQS
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for (i = 0; i < nvec; i++)
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BUG_ON(irq_has_action(entry->irq + i));
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#endif
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}
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arch_teardown_msi_irqs(dev);
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list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
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if (entry->msi_attrib.is_msix) {
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if (list_is_last(&entry->list, &dev->msi_list))
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iounmap(entry->mask_base);
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}
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/*
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* Its possible that we get into this path
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* When populate_msi_sysfs fails, which means the entries
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* were not registered with sysfs. In that case don't
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* unregister them.
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*/
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if (entry->kobj.parent) {
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kobject_del(&entry->kobj);
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kobject_put(&entry->kobj);
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}
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list_del(&entry->list);
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kfree(entry);
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}
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}
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static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
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{
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struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
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if (!desc)
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return NULL;
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INIT_LIST_HEAD(&desc->list);
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desc->dev = dev;
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return desc;
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}
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static void pci_intx_for_msi(struct pci_dev *dev, int enable)
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{
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if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
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pci_intx(dev, enable);
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}
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static void __pci_restore_msi_state(struct pci_dev *dev)
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{
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u16 control;
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struct msi_desc *entry;
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if (!dev->msi_enabled)
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return;
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entry = irq_get_msi_desc(dev->irq);
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pci_intx_for_msi(dev, 0);
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msi_set_enable(dev, 0);
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arch_restore_msi_irqs(dev, dev->irq);
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
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msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
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control &= ~PCI_MSI_FLAGS_QSIZE;
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control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
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pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
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}
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static void __pci_restore_msix_state(struct pci_dev *dev)
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{
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struct msi_desc *entry;
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u16 control;
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if (!dev->msix_enabled)
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return;
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BUG_ON(list_empty(&dev->msi_list));
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entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
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pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
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/* route the table */
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pci_intx_for_msi(dev, 0);
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control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
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pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
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list_for_each_entry(entry, &dev->msi_list, list) {
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arch_restore_msi_irqs(dev, entry->irq);
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msix_mask_irq(entry, entry->masked);
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}
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control &= ~PCI_MSIX_FLAGS_MASKALL;
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pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
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}
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void pci_restore_msi_state(struct pci_dev *dev)
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{
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__pci_restore_msi_state(dev);
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__pci_restore_msix_state(dev);
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}
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EXPORT_SYMBOL_GPL(pci_restore_msi_state);
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#define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr)
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#define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj)
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struct msi_attribute {
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struct attribute attr;
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ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr,
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char *buf);
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ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr,
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const char *buf, size_t count);
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};
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static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr,
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char *buf)
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{
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return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi");
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}
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static ssize_t msi_irq_attr_show(struct kobject *kobj,
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struct attribute *attr, char *buf)
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{
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struct msi_attribute *attribute = to_msi_attr(attr);
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struct msi_desc *entry = to_msi_desc(kobj);
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if (!attribute->show)
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return -EIO;
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return attribute->show(entry, attribute, buf);
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}
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static const struct sysfs_ops msi_irq_sysfs_ops = {
|
|
.show = msi_irq_attr_show,
|
|
};
|
|
|
|
static struct msi_attribute mode_attribute =
|
|
__ATTR(mode, S_IRUGO, show_msi_mode, NULL);
|
|
|
|
|
|
static struct attribute *msi_irq_default_attrs[] = {
|
|
&mode_attribute.attr,
|
|
NULL
|
|
};
|
|
|
|
static void msi_kobj_release(struct kobject *kobj)
|
|
{
|
|
struct msi_desc *entry = to_msi_desc(kobj);
|
|
|
|
pci_dev_put(entry->dev);
|
|
}
|
|
|
|
static struct kobj_type msi_irq_ktype = {
|
|
.release = msi_kobj_release,
|
|
.sysfs_ops = &msi_irq_sysfs_ops,
|
|
.default_attrs = msi_irq_default_attrs,
|
|
};
|
|
|
|
static int populate_msi_sysfs(struct pci_dev *pdev)
|
|
{
|
|
struct msi_desc *entry;
|
|
struct kobject *kobj;
|
|
int ret;
|
|
int count = 0;
|
|
|
|
pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj);
|
|
if (!pdev->msi_kset)
|
|
return -ENOMEM;
|
|
|
|
list_for_each_entry(entry, &pdev->msi_list, list) {
|
|
kobj = &entry->kobj;
|
|
kobj->kset = pdev->msi_kset;
|
|
pci_dev_get(pdev);
|
|
ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL,
|
|
"%u", entry->irq);
|
|
if (ret)
|
|
goto out_unroll;
|
|
|
|
count++;
|
|
}
|
|
|
|
return 0;
|
|
|
|
out_unroll:
|
|
list_for_each_entry(entry, &pdev->msi_list, list) {
|
|
if (!count)
|
|
break;
|
|
kobject_del(&entry->kobj);
|
|
kobject_put(&entry->kobj);
|
|
count--;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* msi_capability_init - configure device's MSI capability structure
|
|
* @dev: pointer to the pci_dev data structure of MSI device function
|
|
* @nvec: number of interrupts to allocate
|
|
*
|
|
* Setup the MSI capability structure of the device with the requested
|
|
* number of interrupts. A return value of zero indicates the successful
|
|
* setup of an entry with the new MSI irq. A negative return value indicates
|
|
* an error, and a positive return value indicates the number of interrupts
|
|
* which could have been allocated.
|
|
*/
|
|
static int msi_capability_init(struct pci_dev *dev, int nvec)
|
|
{
|
|
struct msi_desc *entry;
|
|
int ret;
|
|
u16 control;
|
|
unsigned mask;
|
|
|
|
msi_set_enable(dev, 0); /* Disable MSI during set up */
|
|
|
|
pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
|
|
/* MSI Entry Initialization */
|
|
entry = alloc_msi_entry(dev);
|
|
if (!entry)
|
|
return -ENOMEM;
|
|
|
|
entry->msi_attrib.is_msix = 0;
|
|
entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
|
|
entry->msi_attrib.entry_nr = 0;
|
|
entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
|
|
entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
|
|
entry->msi_attrib.pos = dev->msi_cap;
|
|
|
|
if (control & PCI_MSI_FLAGS_64BIT)
|
|
entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
|
|
else
|
|
entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
|
|
/* All MSIs are unmasked by default, Mask them all */
|
|
if (entry->msi_attrib.maskbit)
|
|
pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
|
|
mask = msi_capable_mask(control);
|
|
msi_mask_irq(entry, mask, mask);
|
|
|
|
list_add_tail(&entry->list, &dev->msi_list);
|
|
|
|
/* Configure MSI capability structure */
|
|
ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
|
|
if (ret) {
|
|
msi_mask_irq(entry, mask, ~mask);
|
|
free_msi_irqs(dev);
|
|
return ret;
|
|
}
|
|
|
|
ret = populate_msi_sysfs(dev);
|
|
if (ret) {
|
|
msi_mask_irq(entry, mask, ~mask);
|
|
free_msi_irqs(dev);
|
|
return ret;
|
|
}
|
|
|
|
/* Set MSI enabled bits */
|
|
pci_intx_for_msi(dev, 0);
|
|
msi_set_enable(dev, 1);
|
|
dev->msi_enabled = 1;
|
|
|
|
dev->irq = entry->irq;
|
|
return 0;
|
|
}
|
|
|
|
static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
|
|
{
|
|
resource_size_t phys_addr;
|
|
u32 table_offset;
|
|
u8 bir;
|
|
|
|
pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
|
|
&table_offset);
|
|
bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
|
|
table_offset &= PCI_MSIX_TABLE_OFFSET;
|
|
phys_addr = pci_resource_start(dev, bir) + table_offset;
|
|
|
|
return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
|
|
}
|
|
|
|
static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
|
|
struct msix_entry *entries, int nvec)
|
|
{
|
|
struct msi_desc *entry;
|
|
int i;
|
|
|
|
for (i = 0; i < nvec; i++) {
|
|
entry = alloc_msi_entry(dev);
|
|
if (!entry) {
|
|
if (!i)
|
|
iounmap(base);
|
|
else
|
|
free_msi_irqs(dev);
|
|
/* No enough memory. Don't try again */
|
|
return -ENOMEM;
|
|
}
|
|
|
|
entry->msi_attrib.is_msix = 1;
|
|
entry->msi_attrib.is_64 = 1;
|
|
entry->msi_attrib.entry_nr = entries[i].entry;
|
|
entry->msi_attrib.default_irq = dev->irq;
|
|
entry->msi_attrib.pos = dev->msix_cap;
|
|
entry->mask_base = base;
|
|
|
|
list_add_tail(&entry->list, &dev->msi_list);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void msix_program_entries(struct pci_dev *dev,
|
|
struct msix_entry *entries)
|
|
{
|
|
struct msi_desc *entry;
|
|
int i = 0;
|
|
|
|
list_for_each_entry(entry, &dev->msi_list, list) {
|
|
int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
|
|
PCI_MSIX_ENTRY_VECTOR_CTRL;
|
|
|
|
entries[i].vector = entry->irq;
|
|
irq_set_msi_desc(entry->irq, entry);
|
|
entry->masked = readl(entry->mask_base + offset);
|
|
msix_mask_irq(entry, 1);
|
|
i++;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* msix_capability_init - configure device's MSI-X capability
|
|
* @dev: pointer to the pci_dev data structure of MSI-X device function
|
|
* @entries: pointer to an array of struct msix_entry entries
|
|
* @nvec: number of @entries
|
|
*
|
|
* Setup the MSI-X capability structure of device function with a
|
|
* single MSI-X irq. A return of zero indicates the successful setup of
|
|
* requested MSI-X entries with allocated irqs or non-zero for otherwise.
|
|
**/
|
|
static int msix_capability_init(struct pci_dev *dev,
|
|
struct msix_entry *entries, int nvec)
|
|
{
|
|
int ret;
|
|
u16 control;
|
|
void __iomem *base;
|
|
|
|
pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
|
|
|
|
/* Ensure MSI-X is disabled while it is set up */
|
|
control &= ~PCI_MSIX_FLAGS_ENABLE;
|
|
pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
|
|
|
|
/* Request & Map MSI-X table region */
|
|
base = msix_map_region(dev, msix_table_size(control));
|
|
if (!base)
|
|
return -ENOMEM;
|
|
|
|
ret = msix_setup_entries(dev, base, entries, nvec);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
|
|
if (ret)
|
|
goto error;
|
|
|
|
/*
|
|
* Some devices require MSI-X to be enabled before we can touch the
|
|
* MSI-X registers. We need to mask all the vectors to prevent
|
|
* interrupts coming in before they're fully set up.
|
|
*/
|
|
control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
|
|
pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
|
|
|
|
msix_program_entries(dev, entries);
|
|
|
|
ret = populate_msi_sysfs(dev);
|
|
if (ret) {
|
|
ret = 0;
|
|
goto error;
|
|
}
|
|
|
|
/* Set MSI-X enabled bits and unmask the function */
|
|
pci_intx_for_msi(dev, 0);
|
|
dev->msix_enabled = 1;
|
|
|
|
control &= ~PCI_MSIX_FLAGS_MASKALL;
|
|
pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
|
|
|
|
return 0;
|
|
|
|
error:
|
|
if (ret < 0) {
|
|
/*
|
|
* If we had some success, report the number of irqs
|
|
* we succeeded in setting up.
|
|
*/
|
|
struct msi_desc *entry;
|
|
int avail = 0;
|
|
|
|
list_for_each_entry(entry, &dev->msi_list, list) {
|
|
if (entry->irq != 0)
|
|
avail++;
|
|
}
|
|
if (avail != 0)
|
|
ret = avail;
|
|
}
|
|
|
|
free_msi_irqs(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* pci_msi_check_device - check whether MSI may be enabled on a device
|
|
* @dev: pointer to the pci_dev data structure of MSI device function
|
|
* @nvec: how many MSIs have been requested ?
|
|
* @type: are we checking for MSI or MSI-X ?
|
|
*
|
|
* Look at global flags, the device itself, and its parent busses
|
|
* to determine if MSI/-X are supported for the device. If MSI/-X is
|
|
* supported return 0, else return an error code.
|
|
**/
|
|
static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
|
|
{
|
|
struct pci_bus *bus;
|
|
int ret;
|
|
|
|
/* MSI must be globally enabled and supported by the device */
|
|
if (!pci_msi_enable || !dev || dev->no_msi)
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* You can't ask to have 0 or less MSIs configured.
|
|
* a) it's stupid ..
|
|
* b) the list manipulation code assumes nvec >= 1.
|
|
*/
|
|
if (nvec < 1)
|
|
return -ERANGE;
|
|
|
|
/*
|
|
* Any bridge which does NOT route MSI transactions from its
|
|
* secondary bus to its primary bus must set NO_MSI flag on
|
|
* the secondary pci_bus.
|
|
* We expect only arch-specific PCI host bus controller driver
|
|
* or quirks for specific PCI bridges to be setting NO_MSI.
|
|
*/
|
|
for (bus = dev->bus; bus; bus = bus->parent)
|
|
if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
|
|
return -EINVAL;
|
|
|
|
ret = arch_msi_check_device(dev, nvec, type);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* pci_enable_msi_block - configure device's MSI capability structure
|
|
* @dev: device to configure
|
|
* @nvec: number of interrupts to configure
|
|
*
|
|
* Allocate IRQs for a device with the MSI capability.
|
|
* This function returns a negative errno if an error occurs. If it
|
|
* is unable to allocate the number of interrupts requested, it returns
|
|
* the number of interrupts it might be able to allocate. If it successfully
|
|
* allocates at least the number of interrupts requested, it returns 0 and
|
|
* updates the @dev's irq member to the lowest new interrupt number; the
|
|
* other interrupt numbers allocated to this device are consecutive.
|
|
*/
|
|
int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
|
|
{
|
|
int status, maxvec;
|
|
u16 msgctl;
|
|
|
|
if (!dev->msi_cap)
|
|
return -EINVAL;
|
|
|
|
pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
|
|
maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
|
|
if (nvec > maxvec)
|
|
return maxvec;
|
|
|
|
status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
|
|
if (status)
|
|
return status;
|
|
|
|
WARN_ON(!!dev->msi_enabled);
|
|
|
|
/* Check whether driver already requested MSI-X irqs */
|
|
if (dev->msix_enabled) {
|
|
dev_info(&dev->dev, "can't enable MSI "
|
|
"(MSI-X already enabled)\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
status = msi_capability_init(dev, nvec);
|
|
return status;
|
|
}
|
|
EXPORT_SYMBOL(pci_enable_msi_block);
|
|
|
|
int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
|
|
{
|
|
int ret, nvec;
|
|
u16 msgctl;
|
|
|
|
if (!dev->msi_cap)
|
|
return -EINVAL;
|
|
|
|
pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
|
|
ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
|
|
|
|
if (maxvec)
|
|
*maxvec = ret;
|
|
|
|
do {
|
|
nvec = ret;
|
|
ret = pci_enable_msi_block(dev, nvec);
|
|
} while (ret > 0);
|
|
|
|
if (ret < 0)
|
|
return ret;
|
|
return nvec;
|
|
}
|
|
EXPORT_SYMBOL(pci_enable_msi_block_auto);
|
|
|
|
void pci_msi_shutdown(struct pci_dev *dev)
|
|
{
|
|
struct msi_desc *desc;
|
|
u32 mask;
|
|
u16 ctrl;
|
|
|
|
if (!pci_msi_enable || !dev || !dev->msi_enabled)
|
|
return;
|
|
|
|
BUG_ON(list_empty(&dev->msi_list));
|
|
desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
|
|
|
|
msi_set_enable(dev, 0);
|
|
pci_intx_for_msi(dev, 1);
|
|
dev->msi_enabled = 0;
|
|
|
|
/* Return the device with MSI unmasked as initial states */
|
|
pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl);
|
|
mask = msi_capable_mask(ctrl);
|
|
/* Keep cached state to be restored */
|
|
__msi_mask_irq(desc, mask, ~mask);
|
|
|
|
/* Restore dev->irq to its default pin-assertion irq */
|
|
dev->irq = desc->msi_attrib.default_irq;
|
|
}
|
|
|
|
void pci_disable_msi(struct pci_dev *dev)
|
|
{
|
|
if (!pci_msi_enable || !dev || !dev->msi_enabled)
|
|
return;
|
|
|
|
pci_msi_shutdown(dev);
|
|
free_msi_irqs(dev);
|
|
kset_unregister(dev->msi_kset);
|
|
dev->msi_kset = NULL;
|
|
}
|
|
EXPORT_SYMBOL(pci_disable_msi);
|
|
|
|
/**
|
|
* pci_msix_table_size - return the number of device's MSI-X table entries
|
|
* @dev: pointer to the pci_dev data structure of MSI-X device function
|
|
*/
|
|
int pci_msix_table_size(struct pci_dev *dev)
|
|
{
|
|
u16 control;
|
|
|
|
if (!dev->msix_cap)
|
|
return 0;
|
|
|
|
pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
|
|
return msix_table_size(control);
|
|
}
|
|
|
|
/**
|
|
* pci_enable_msix - configure device's MSI-X capability structure
|
|
* @dev: pointer to the pci_dev data structure of MSI-X device function
|
|
* @entries: pointer to an array of MSI-X entries
|
|
* @nvec: number of MSI-X irqs requested for allocation by device driver
|
|
*
|
|
* Setup the MSI-X capability structure of device function with the number
|
|
* of requested irqs upon its software driver call to request for
|
|
* MSI-X mode enabled on its hardware device function. A return of zero
|
|
* indicates the successful configuration of MSI-X capability structure
|
|
* with new allocated MSI-X irqs. A return of < 0 indicates a failure.
|
|
* Or a return of > 0 indicates that driver request is exceeding the number
|
|
* of irqs or MSI-X vectors available. Driver should use the returned value to
|
|
* re-send its request.
|
|
**/
|
|
int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
|
|
{
|
|
int status, nr_entries;
|
|
int i, j;
|
|
|
|
if (!entries || !dev->msix_cap)
|
|
return -EINVAL;
|
|
|
|
status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
|
|
if (status)
|
|
return status;
|
|
|
|
nr_entries = pci_msix_table_size(dev);
|
|
if (nvec > nr_entries)
|
|
return nr_entries;
|
|
|
|
/* Check for any invalid entries */
|
|
for (i = 0; i < nvec; i++) {
|
|
if (entries[i].entry >= nr_entries)
|
|
return -EINVAL; /* invalid entry */
|
|
for (j = i + 1; j < nvec; j++) {
|
|
if (entries[i].entry == entries[j].entry)
|
|
return -EINVAL; /* duplicate entry */
|
|
}
|
|
}
|
|
WARN_ON(!!dev->msix_enabled);
|
|
|
|
/* Check whether driver already requested for MSI irq */
|
|
if (dev->msi_enabled) {
|
|
dev_info(&dev->dev, "can't enable MSI-X "
|
|
"(MSI IRQ already assigned)\n");
|
|
return -EINVAL;
|
|
}
|
|
status = msix_capability_init(dev, entries, nvec);
|
|
return status;
|
|
}
|
|
EXPORT_SYMBOL(pci_enable_msix);
|
|
|
|
void pci_msix_shutdown(struct pci_dev *dev)
|
|
{
|
|
struct msi_desc *entry;
|
|
|
|
if (!pci_msi_enable || !dev || !dev->msix_enabled)
|
|
return;
|
|
|
|
/* Return the device with MSI-X masked as initial states */
|
|
list_for_each_entry(entry, &dev->msi_list, list) {
|
|
/* Keep cached states to be restored */
|
|
__msix_mask_irq(entry, 1);
|
|
}
|
|
|
|
msix_set_enable(dev, 0);
|
|
pci_intx_for_msi(dev, 1);
|
|
dev->msix_enabled = 0;
|
|
}
|
|
|
|
void pci_disable_msix(struct pci_dev *dev)
|
|
{
|
|
if (!pci_msi_enable || !dev || !dev->msix_enabled)
|
|
return;
|
|
|
|
pci_msix_shutdown(dev);
|
|
free_msi_irqs(dev);
|
|
kset_unregister(dev->msi_kset);
|
|
dev->msi_kset = NULL;
|
|
}
|
|
EXPORT_SYMBOL(pci_disable_msix);
|
|
|
|
/**
|
|
* msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
|
|
* @dev: pointer to the pci_dev data structure of MSI(X) device function
|
|
*
|
|
* Being called during hotplug remove, from which the device function
|
|
* is hot-removed. All previous assigned MSI/MSI-X irqs, if
|
|
* allocated for this device function, are reclaimed to unused state,
|
|
* which may be used later on.
|
|
**/
|
|
void msi_remove_pci_irq_vectors(struct pci_dev *dev)
|
|
{
|
|
if (!pci_msi_enable || !dev)
|
|
return;
|
|
|
|
if (dev->msi_enabled || dev->msix_enabled)
|
|
free_msi_irqs(dev);
|
|
}
|
|
|
|
void pci_no_msi(void)
|
|
{
|
|
pci_msi_enable = 0;
|
|
}
|
|
|
|
/**
|
|
* pci_msi_enabled - is MSI enabled?
|
|
*
|
|
* Returns true if MSI has not been disabled by the command-line option
|
|
* pci=nomsi.
|
|
**/
|
|
int pci_msi_enabled(void)
|
|
{
|
|
return pci_msi_enable;
|
|
}
|
|
EXPORT_SYMBOL(pci_msi_enabled);
|
|
|
|
void pci_msi_init_pci_dev(struct pci_dev *dev)
|
|
{
|
|
INIT_LIST_HEAD(&dev->msi_list);
|
|
|
|
/* Disable the msi hardware to avoid screaming interrupts
|
|
* during boot. This is the power on reset default so
|
|
* usually this should be a noop.
|
|
*/
|
|
dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
|
|
if (dev->msi_cap)
|
|
msi_set_enable(dev, 0);
|
|
|
|
dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
|
|
if (dev->msix_cap)
|
|
msix_set_enable(dev, 0);
|
|
}
|