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b543c301c2
Add RX DMA transfers support for samsung serial driver. It's enabled when DMA controller for RX channel is specified in device-tree. DMA transactions are started when number of bytes in RX FIFO reaches trigger level, otherwise PIO mode is used. DMA transfer size is always PAGE_SIZE which can cause large latency when smaller data amount is transferred, so we always terminate DMA transaction on RX timeout interrupt. Timeout interval is set to 64 frame times. Based on previous work of Sylwester Nawrocki and Lukasz Czerwinski. Signed-off-by: Robert Baldyga <r.baldyga@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
126 lines
2.8 KiB
C
126 lines
2.8 KiB
C
#ifndef __SAMSUNG_H
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#define __SAMSUNG_H
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/*
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* Driver for Samsung SoC onboard UARTs.
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*
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* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/dmaengine.h>
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struct s3c24xx_uart_info {
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char *name;
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unsigned int type;
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unsigned int fifosize;
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unsigned long rx_fifomask;
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unsigned long rx_fifoshift;
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unsigned long rx_fifofull;
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unsigned long tx_fifomask;
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unsigned long tx_fifoshift;
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unsigned long tx_fifofull;
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unsigned int def_clk_sel;
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unsigned long num_clks;
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unsigned long clksel_mask;
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unsigned long clksel_shift;
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/* uart port features */
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unsigned int has_divslot:1;
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/* uart controls */
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int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
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};
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struct s3c24xx_serial_drv_data {
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struct s3c24xx_uart_info *info;
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struct s3c2410_uartcfg *def_cfg;
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unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
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};
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struct s3c24xx_uart_dma {
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dma_filter_fn fn;
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void *rx_param;
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void *tx_param;
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unsigned int rx_chan_id;
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unsigned int tx_chan_id;
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struct dma_slave_config rx_conf;
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struct dma_slave_config tx_conf;
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struct dma_chan *rx_chan;
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struct dma_chan *tx_chan;
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dma_addr_t rx_addr;
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dma_addr_t tx_addr;
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dma_cookie_t rx_cookie;
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dma_cookie_t tx_cookie;
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char *rx_buf;
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dma_addr_t tx_transfer_addr;
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size_t rx_size;
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size_t tx_size;
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struct dma_async_tx_descriptor *tx_desc;
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struct dma_async_tx_descriptor *rx_desc;
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int tx_bytes_requested;
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int rx_bytes_requested;
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};
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struct s3c24xx_uart_port {
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unsigned char rx_claimed;
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unsigned char tx_claimed;
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unsigned int pm_level;
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unsigned long baudclk_rate;
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unsigned int rx_irq;
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unsigned int tx_irq;
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unsigned int tx_in_progress;
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unsigned int tx_mode;
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unsigned int rx_mode;
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struct s3c24xx_uart_info *info;
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struct clk *clk;
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struct clk *baudclk;
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struct uart_port port;
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struct s3c24xx_serial_drv_data *drv_data;
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/* reference to platform data */
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struct s3c2410_uartcfg *cfg;
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struct s3c24xx_uart_dma *dma;
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#ifdef CONFIG_CPU_FREQ
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struct notifier_block freq_transition;
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#endif
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};
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/* conversion functions */
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#define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
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/* register access controls */
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#define portaddr(port, reg) ((port)->membase + (reg))
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#define portaddrl(port, reg) \
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((unsigned long *)(unsigned long)((port)->membase + (reg)))
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#define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
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#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
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#define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
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#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
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#endif
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