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bd809af16e
Update the translation tables from cache mode to pgprot values according to the PAT settings. This enables changing the cache attributes of a PAT index in just one place without having to change at the users side. With this change it is possible to use the same kernel with different PAT configurations, e.g. supporting Xen. Signed-off-by: Juergen Gross <jgross@suse.com> Reviewed-by: Toshi Kani <toshi.kani@hp.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Cc: stefan.bader@canonical.com Cc: xen-devel@lists.xensource.com Cc: ville.syrjala@linux.intel.com Cc: david.vrabel@citrix.com Cc: jbeulich@suse.com Cc: plagnioj@jcrosoft.com Cc: tomi.valkeinen@ti.com Cc: bhelgaas@google.com Link: http://lkml.kernel.org/r/1415019724-4317-18-git-send-email-jgross@suse.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
22 lines
519 B
C
22 lines
519 B
C
#ifndef __X86_MM_INTERNAL_H
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#define __X86_MM_INTERNAL_H
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void *alloc_low_pages(unsigned int num);
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static inline void *alloc_low_page(void)
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{
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return alloc_low_pages(1);
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}
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void early_ioremap_page_table_range_init(void);
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unsigned long kernel_physical_mapping_init(unsigned long start,
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unsigned long end,
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unsigned long page_size_mask);
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void zone_sizes_init(void);
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extern int after_bootmem;
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void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache);
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#endif /* __X86_MM_INTERNAL_H */
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