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https://github.com/edk2-porting/linux-next.git
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f7b81d67d0
Add the NSS/GMAC clocks and the TCM clock and NSS resets. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> Signed-off-by: David S. Miller <davem@davemloft.net>
176 lines
5.7 KiB
C
176 lines
5.7 KiB
C
/*
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_RESET_IPQ_806X_H
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#define _DT_BINDINGS_RESET_IPQ_806X_H
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#define QDSS_STM_RESET 0
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#define AFAB_SMPSS_S_RESET 1
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#define AFAB_SMPSS_M1_RESET 2
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#define AFAB_SMPSS_M0_RESET 3
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#define AFAB_EBI1_CH0_RESET 4
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#define AFAB_EBI1_CH1_RESET 5
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#define SFAB_ADM0_M0_RESET 6
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#define SFAB_ADM0_M1_RESET 7
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#define SFAB_ADM0_M2_RESET 8
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#define ADM0_C2_RESET 9
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#define ADM0_C1_RESET 10
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#define ADM0_C0_RESET 11
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#define ADM0_PBUS_RESET 12
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#define ADM0_RESET 13
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#define QDSS_CLKS_SW_RESET 14
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#define QDSS_POR_RESET 15
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#define QDSS_TSCTR_RESET 16
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#define QDSS_HRESET_RESET 17
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#define QDSS_AXI_RESET 18
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#define QDSS_DBG_RESET 19
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#define SFAB_PCIE_M_RESET 20
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#define SFAB_PCIE_S_RESET 21
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#define PCIE_EXT_RESET 22
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#define PCIE_PHY_RESET 23
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#define PCIE_PCI_RESET 24
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#define PCIE_POR_RESET 25
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#define PCIE_HCLK_RESET 26
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#define PCIE_ACLK_RESET 27
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#define SFAB_LPASS_RESET 28
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#define SFAB_AFAB_M_RESET 29
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#define AFAB_SFAB_M0_RESET 30
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#define AFAB_SFAB_M1_RESET 31
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#define SFAB_SATA_S_RESET 32
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#define SFAB_DFAB_M_RESET 33
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#define DFAB_SFAB_M_RESET 34
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#define DFAB_SWAY0_RESET 35
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#define DFAB_SWAY1_RESET 36
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#define DFAB_ARB0_RESET 37
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#define DFAB_ARB1_RESET 38
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#define PPSS_PROC_RESET 39
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#define PPSS_RESET 40
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#define DMA_BAM_RESET 41
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#define SPS_TIC_H_RESET 42
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#define SFAB_CFPB_M_RESET 43
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#define SFAB_CFPB_S_RESET 44
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#define TSIF_H_RESET 45
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#define CE1_H_RESET 46
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#define CE1_CORE_RESET 47
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#define CE1_SLEEP_RESET 48
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#define CE2_H_RESET 49
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#define CE2_CORE_RESET 50
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#define SFAB_SFPB_M_RESET 51
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#define SFAB_SFPB_S_RESET 52
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#define RPM_PROC_RESET 53
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#define PMIC_SSBI2_RESET 54
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#define SDC1_RESET 55
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#define SDC2_RESET 56
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#define SDC3_RESET 57
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#define SDC4_RESET 58
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#define USB_HS1_RESET 59
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#define USB_HSIC_RESET 60
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#define USB_FS1_XCVR_RESET 61
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#define USB_FS1_RESET 62
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#define GSBI1_RESET 63
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#define GSBI2_RESET 64
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#define GSBI3_RESET 65
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#define GSBI4_RESET 66
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#define GSBI5_RESET 67
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#define GSBI6_RESET 68
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#define GSBI7_RESET 69
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#define SPDM_RESET 70
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#define SEC_CTRL_RESET 71
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#define TLMM_H_RESET 72
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#define SFAB_SATA_M_RESET 73
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#define SATA_RESET 74
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#define TSSC_RESET 75
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#define PDM_RESET 76
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#define MPM_H_RESET 77
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#define MPM_RESET 78
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#define SFAB_SMPSS_S_RESET 79
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#define PRNG_RESET 80
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#define SFAB_CE3_M_RESET 81
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#define SFAB_CE3_S_RESET 82
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#define CE3_SLEEP_RESET 83
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#define PCIE_1_M_RESET 84
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#define PCIE_1_S_RESET 85
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#define PCIE_1_EXT_RESET 86
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#define PCIE_1_PHY_RESET 87
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#define PCIE_1_PCI_RESET 88
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#define PCIE_1_POR_RESET 89
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#define PCIE_1_HCLK_RESET 90
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#define PCIE_1_ACLK_RESET 91
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#define PCIE_2_M_RESET 92
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#define PCIE_2_S_RESET 93
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#define PCIE_2_EXT_RESET 94
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#define PCIE_2_PHY_RESET 95
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#define PCIE_2_PCI_RESET 96
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#define PCIE_2_POR_RESET 97
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#define PCIE_2_HCLK_RESET 98
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#define PCIE_2_ACLK_RESET 99
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#define SFAB_USB30_S_RESET 100
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#define SFAB_USB30_M_RESET 101
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#define USB30_0_PORT2_HS_PHY_RESET 102
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#define USB30_0_MASTER_RESET 103
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#define USB30_0_SLEEP_RESET 104
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#define USB30_0_UTMI_PHY_RESET 105
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#define USB30_0_POWERON_RESET 106
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#define USB30_0_PHY_RESET 107
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#define USB30_1_MASTER_RESET 108
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#define USB30_1_SLEEP_RESET 109
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#define USB30_1_UTMI_PHY_RESET 110
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#define USB30_1_POWERON_RESET 111
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#define USB30_1_PHY_RESET 112
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#define NSSFB0_RESET 113
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#define NSSFB1_RESET 114
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#define UBI32_CORE1_CLKRST_CLAMP_RESET 115
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#define UBI32_CORE1_CLAMP_RESET 116
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#define UBI32_CORE1_AHB_RESET 117
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#define UBI32_CORE1_AXI_RESET 118
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#define UBI32_CORE2_CLKRST_CLAMP_RESET 119
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#define UBI32_CORE2_CLAMP_RESET 120
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#define UBI32_CORE2_AHB_RESET 121
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#define UBI32_CORE2_AXI_RESET 122
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#define GMAC_CORE1_RESET 123
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#define GMAC_CORE2_RESET 124
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#define GMAC_CORE3_RESET 125
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#define GMAC_CORE4_RESET 126
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#define GMAC_AHB_RESET 127
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#define NSS_CH0_RST_RX_CLK_N_RESET 128
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#define NSS_CH0_RST_TX_CLK_N_RESET 129
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#define NSS_CH0_RST_RX_125M_N_RESET 130
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#define NSS_CH0_HW_RST_RX_125M_N_RESET 131
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#define NSS_CH0_RST_TX_125M_N_RESET 132
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#define NSS_CH1_RST_RX_CLK_N_RESET 133
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#define NSS_CH1_RST_TX_CLK_N_RESET 134
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#define NSS_CH1_RST_RX_125M_N_RESET 135
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#define NSS_CH1_HW_RST_RX_125M_N_RESET 136
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#define NSS_CH1_RST_TX_125M_N_RESET 137
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#define NSS_CH2_RST_RX_CLK_N_RESET 138
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#define NSS_CH2_RST_TX_CLK_N_RESET 139
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#define NSS_CH2_RST_RX_125M_N_RESET 140
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#define NSS_CH2_HW_RST_RX_125M_N_RESET 141
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#define NSS_CH2_RST_TX_125M_N_RESET 142
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#define NSS_CH3_RST_RX_CLK_N_RESET 143
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#define NSS_CH3_RST_TX_CLK_N_RESET 144
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#define NSS_CH3_RST_RX_125M_N_RESET 145
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#define NSS_CH3_HW_RST_RX_125M_N_RESET 146
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#define NSS_CH3_RST_TX_125M_N_RESET 147
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#define NSS_RST_RX_250M_125M_N_RESET 148
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#define NSS_RST_TX_250M_125M_N_RESET 149
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#define NSS_QSGMII_TXPI_RST_N_RESET 150
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#define NSS_QSGMII_CDR_RST_N_RESET 151
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#define NSS_SGMII2_CDR_RST_N_RESET 152
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#define NSS_SGMII3_CDR_RST_N_RESET 153
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#define NSS_CAL_PRBS_RST_N_RESET 154
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#define NSS_LCKDT_RST_N_RESET 155
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#define NSS_SRDS_N_RESET 156
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#endif
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