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0e2be4c112
The SMP boot on Armada 38x and Armada 375 Z1 is currently broken in big-endian configurations, and this commit fixes it for both platforms. For Armada 375 Z1, the problem was in the armada_375_smp_cpu1_enable_code part of the code that gets copied to the Crypto SRAM as a work-around for an issue of the Z1 stepping. This piece of code was not switching the CPU core to big-endian, and not endian-swapping the value read from the Resume Address register (the value is stored little-endian). Due to the introduction of the conditional 'rev r1, r1' instruction, the offset between the 'ldr r0, [pc, #4]' instruction and the value it was looking is different between LE and BE configurations. To solve this, we instead use one 'adr' instruction followed by one 'ldr'. For Armada 38x, the problem was simply that the CPU core was not switched to big endian in the secondary CPU startup function. This change was tested in LE and BE configurations on Armada 385, Armada 375 Z1 and Armada 375 A0. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1404228186-21203-1-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
42 lines
1.0 KiB
ArmAsm
42 lines
1.0 KiB
ArmAsm
/*
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* SMP support: Entry point for secondary CPUs of Marvell EBU
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* Cortex-A9 based SOCs (Armada 375 and Armada 38x).
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*
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* Copyright (C) 2014 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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__CPUINIT
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#define CPU_RESUME_ADDR_REG 0xf10182d4
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.global armada_375_smp_cpu1_enable_code_start
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.global armada_375_smp_cpu1_enable_code_end
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armada_375_smp_cpu1_enable_code_start:
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ARM_BE8(setend be)
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adr r0, 1f
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ldr r0, [r0]
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ldr r1, [r0]
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ARM_BE8(rev r1, r1)
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mov pc, r1
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1:
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.word CPU_RESUME_ADDR_REG
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armada_375_smp_cpu1_enable_code_end:
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ENTRY(mvebu_cortex_a9_secondary_startup)
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ARM_BE8(setend be)
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bl v7_invalidate_l1
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b secondary_startup
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ENDPROC(mvebu_cortex_a9_secondary_startup)
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