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Add support for Actions Semi composite clock. This clock consists of gate, mux, divider, factor and fixed factor clocks. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
125 lines
3.1 KiB
C
125 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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//
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// OWL composite clock driver
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//
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// Copyright (c) 2014 Actions Semi Inc.
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// Author: David Liu <liuwei@actions-semi.com>
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//
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// Copyright (c) 2018 Linaro Ltd.
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// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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#ifndef _OWL_COMPOSITE_H_
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#define _OWL_COMPOSITE_H_
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#include "owl-common.h"
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#include "owl-mux.h"
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#include "owl-gate.h"
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#include "owl-factor.h"
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#include "owl-fixed-factor.h"
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#include "owl-divider.h"
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union owl_rate {
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struct owl_divider_hw div_hw;
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struct owl_factor_hw factor_hw;
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struct clk_fixed_factor fix_fact_hw;
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};
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struct owl_composite {
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struct owl_mux_hw mux_hw;
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struct owl_gate_hw gate_hw;
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union owl_rate rate;
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const struct clk_ops *fix_fact_ops;
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struct owl_clk_common common;
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};
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#define OWL_COMP_DIV(_struct, _name, _parent, \
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_mux, _gate, _div, _flags) \
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struct owl_composite _struct = { \
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.mux_hw = _mux, \
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.gate_hw = _gate, \
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.rate.div_hw = _div, \
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.common = { \
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.regmap = NULL, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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_parent, \
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&owl_comp_div_ops,\
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_flags), \
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}, \
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}
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#define OWL_COMP_DIV_FIXED(_struct, _name, _parent, \
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_gate, _div, _flags) \
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struct owl_composite _struct = { \
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.gate_hw = _gate, \
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.rate.div_hw = _div, \
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.common = { \
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.regmap = NULL, \
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.hw.init = CLK_HW_INIT(_name, \
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_parent, \
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&owl_comp_div_ops,\
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_flags), \
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}, \
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}
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#define OWL_COMP_FACTOR(_struct, _name, _parent, \
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_mux, _gate, _factor, _flags) \
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struct owl_composite _struct = { \
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.mux_hw = _mux, \
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.gate_hw = _gate, \
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.rate.factor_hw = _factor, \
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.common = { \
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.regmap = NULL, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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_parent, \
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&owl_comp_fact_ops,\
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_flags), \
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}, \
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}
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#define OWL_COMP_FIXED_FACTOR(_struct, _name, _parent, \
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_gate, _mul, _div, _flags) \
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struct owl_composite _struct = { \
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.gate_hw = _gate, \
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.rate.fix_fact_hw.mult = _mul, \
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.rate.fix_fact_hw.div = _div, \
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.fix_fact_ops = &clk_fixed_factor_ops, \
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.common = { \
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.regmap = NULL, \
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.hw.init = CLK_HW_INIT(_name, \
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_parent, \
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&owl_comp_fix_fact_ops,\
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_flags), \
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}, \
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}
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#define OWL_COMP_PASS(_struct, _name, _parent, \
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_mux, _gate, _flags) \
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struct owl_composite _struct = { \
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.mux_hw = _mux, \
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.gate_hw = _gate, \
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.common = { \
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.regmap = NULL, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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_parent, \
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&owl_comp_pass_ops,\
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_flags), \
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}, \
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}
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static inline struct owl_composite *hw_to_owl_comp(const struct clk_hw *hw)
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{
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struct owl_clk_common *common = hw_to_owl_clk_common(hw);
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return container_of(common, struct owl_composite, common);
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}
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extern const struct clk_ops owl_comp_div_ops;
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extern const struct clk_ops owl_comp_fact_ops;
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extern const struct clk_ops owl_comp_fix_fact_ops;
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extern const struct clk_ops owl_comp_pass_ops;
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extern const struct clk_ops clk_fixed_factor_ops;
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#endif /* _OWL_COMPOSITE_H_ */
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