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74c32e7234
The body of the mach-ixp4xx arch_idle() is mysteriously disabled by an #if 0 .. #endif. Normally one would expect to find a call to cpu_do_idle() there, but that call is disabled, even though cpu_do_idle() is implemented for XScale cores (and ixp4xx is one). The explanation can be found in the ixp42x developer's manual which states that the XScale core clock and power management registers aren't implemented on ixp42x [3.5.2.2]. Also, the disabled code has suffered from bit rot: - it checks hlt_counter which is obsolete, as that variable and all related code now is private to kernel/process.c - it passes too many parameters to cpu_do_idle() So this patch: - adds a comment before the #if 0 to explain why cpu_do_idle() mustn't be called on ixp4xx - removes the obsolete test of hlt_counter and the obsolete parameter to cpu_do_idle() This is purely a documentation fixup and changes no generated code. Even so, it has been tested on an ixp420 machine (ds101). Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
45 lines
962 B
C
45 lines
962 B
C
/*
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* arch/arm/mach-ixp4xx/include/mach/system.h
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*
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* Copyright (C) 2002 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <mach/hardware.h>
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static inline void arch_idle(void)
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{
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/* ixp4xx does not implement the XScale PWRMODE register,
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* so it must not call cpu_do_idle() here.
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*/
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#if 0
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cpu_do_idle();
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#endif
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}
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static inline void arch_reset(char mode, const char *cmd)
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{
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if ( 1 && mode == 's') {
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/* Jump into ROM at address 0 */
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cpu_reset(0);
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} else {
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/* Use on-chip reset capability */
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/* set the "key" register to enable access to
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* "timer" and "enable" registers
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*/
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*IXP4XX_OSWK = IXP4XX_WDT_KEY;
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/* write 0 to the timer register for an immediate reset */
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*IXP4XX_OSWT = 0;
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*IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
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}
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}
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