mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-27 14:43:58 +08:00
6845664a6a
Convert to the new function names. Automated with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
112 lines
2.3 KiB
C
112 lines
2.3 KiB
C
/*
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* Copyright (C) Telechips, Inc.
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* Copyright (C) 2009-2010 Hans J. Koch <hjk@linutronix.de>
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*
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* Licensed under the terms of the GNU GPL version 2.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <mach/tcc8k-regs.h>
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#include <mach/irqs.h>
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#include "common.h"
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/* Disable IRQ */
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static void tcc8000_mask_ack_irq0(struct irq_data *d)
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{
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PIC0_IEN &= ~(1 << d->irq);
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PIC0_CREQ |= (1 << d->irq);
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}
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static void tcc8000_mask_ack_irq1(struct irq_data *d)
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{
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PIC1_IEN &= ~(1 << (d->irq - 32));
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PIC1_CREQ |= (1 << (d->irq - 32));
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}
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static void tcc8000_mask_irq0(struct irq_data *d)
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{
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PIC0_IEN &= ~(1 << d->irq);
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}
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static void tcc8000_mask_irq1(struct irq_data *d)
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{
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PIC1_IEN &= ~(1 << (d->irq - 32));
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}
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static void tcc8000_ack_irq0(struct irq_data *d)
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{
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PIC0_CREQ |= (1 << d->irq);
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}
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static void tcc8000_ack_irq1(struct irq_data *d)
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{
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PIC1_CREQ |= (1 << (d->irq - 32));
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}
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/* Enable IRQ */
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static void tcc8000_unmask_irq0(struct irq_data *d)
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{
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PIC0_IEN |= (1 << d->irq);
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PIC0_INTOEN |= (1 << d->irq);
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}
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static void tcc8000_unmask_irq1(struct irq_data *d)
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{
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PIC1_IEN |= (1 << (d->irq - 32));
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PIC1_INTOEN |= (1 << (d->irq - 32));
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}
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static struct irq_chip tcc8000_irq_chip0 = {
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.name = "tcc_irq0",
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.irq_mask = tcc8000_mask_irq0,
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.irq_ack = tcc8000_ack_irq0,
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.irq_mask_ack = tcc8000_mask_ack_irq0,
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.irq_unmask = tcc8000_unmask_irq0,
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};
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static struct irq_chip tcc8000_irq_chip1 = {
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.name = "tcc_irq1",
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.irq_mask = tcc8000_mask_irq1,
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.irq_ack = tcc8000_ack_irq1,
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.irq_mask_ack = tcc8000_mask_ack_irq1,
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.irq_unmask = tcc8000_unmask_irq1,
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};
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void __init tcc8k_init_irq(void)
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{
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int irqno;
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/* Mask and clear all interrupts */
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PIC0_IEN = 0x00000000;
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PIC0_CREQ = 0xffffffff;
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PIC1_IEN = 0x00000000;
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PIC1_CREQ = 0xffffffff;
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PIC0_MEN0 = 0x00000003;
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PIC1_MEN1 = 0x00000003;
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PIC1_MEN = 0x00000003;
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/* let all IRQs be level triggered */
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PIC0_TMODE = 0xffffffff;
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PIC1_TMODE = 0xffffffff;
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/* all IRQs are IRQs (not FIQs) */
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PIC0_IRQSEL = 0xffffffff;
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PIC1_IRQSEL = 0xffffffff;
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for (irqno = 0; irqno < NR_IRQS; irqno++) {
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if (irqno < 32)
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irq_set_chip(irqno, &tcc8000_irq_chip0);
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else
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irq_set_chip(irqno, &tcc8000_irq_chip1);
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irq_set_handler(irqno, handle_level_irq);
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set_irq_flags(irqno, IRQF_VALID);
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}
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}
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