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This adds the clock binding documentation for the Marvell PXA1928 SOC. The PXA1928 has 3 clock control blocks for different subsystems of the chip. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
22 lines
870 B
Plaintext
22 lines
870 B
Plaintext
* Marvell PXA1928 Clock Controllers
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The PXA1928 clock subsystem generates and supplies clock to various
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controllers within the PXA1928 SoC. The PXA1928 contains 3 clock controller
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blocks called APMU, MPMU, and APBC roughly corresponding to internal buses.
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Required Properties:
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- compatible: should be one of the following.
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- "marvell,pxa1928-apmu" - APMU controller compatible
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- "marvell,pxa1928-mpmu" - MPMU controller compatible
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- "marvell,pxa1928-apbc" - APBC controller compatible
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- reg: physical base address of the clock controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Each clock is assigned an identifier and client nodes use the clock controller
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phandle and this identifier to specify the clock which they consume.
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All these identifiers can be found in <dt-bindings/clock/marvell,pxa1928.h>.
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