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9a761e4368
This patch adds a set of core files of the Exynos4x12 FIMC-IS V4L2 driver. This includes main functionality like allocating memory, loading the firmware, FIMC-IS register interface and host CPU <-> IS command and error code definitions. The driver currently exposes a single subdev named FIMC-IS-ISP, which corresponds to the FIMC-IS ISP and DRC IP blocks. The FIMC-IS-ISP subdev currently supports only a subset of user controls. For other controls we need several extensions at the V4L2 API. The supported standard controls are: brightness, contrast, saturation, hue, sharpness, 3a_lock, exposure_time_absolute, white_balance_auto_preset, iso_sensitivity, iso_sensitivity_auto, exposure_metering_mode. Signed-off-by: Younghwan Joo <yhwan.joo@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
138 lines
2.9 KiB
C
138 lines
2.9 KiB
C
/*
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* Samsung Exynos4x12 FIMC-IS (Imaging Subsystem) driver
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*
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* FIMC-IS command set definitions
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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*
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* Authors: Younghwan Joo <yhwan.joo@samsung.com>
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* Sylwester Nawrocki <s.nawrocki@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef FIMC_IS_CMD_H_
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#define FIMC_IS_CMD_H_
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#define FIMC_IS_COMMAND_VER 110 /* FIMC-IS command set version 1.10 */
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/* Enumeration of commands beetween the FIMC-IS and the host processor. */
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/* HOST to FIMC-IS */
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#define HIC_PREVIEW_STILL 0x0001
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#define HIC_PREVIEW_VIDEO 0x0002
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#define HIC_CAPTURE_STILL 0x0003
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#define HIC_CAPTURE_VIDEO 0x0004
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#define HIC_STREAM_ON 0x0005
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#define HIC_STREAM_OFF 0x0006
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#define HIC_SET_PARAMETER 0x0007
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#define HIC_GET_PARAMETER 0x0008
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#define HIC_SET_TUNE 0x0009
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#define HIC_GET_STATUS 0x000b
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/* Sensor part */
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#define HIC_OPEN_SENSOR 0x000c
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#define HIC_CLOSE_SENSOR 0x000d
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#define HIC_SIMMIAN_INIT 0x000e
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#define HIC_SIMMIAN_WRITE 0x000f
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#define HIC_SIMMIAN_READ 0x0010
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#define HIC_POWER_DOWN 0x0011
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#define HIC_GET_SET_FILE_ADDR 0x0012
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#define HIC_LOAD_SET_FILE 0x0013
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#define HIC_MSG_CONFIG 0x0014
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#define HIC_MSG_TEST 0x0015
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/* FIMC-IS to HOST */
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#define IHC_GET_SENSOR_NUM 0x1000
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#define IHC_SET_SHOT_MARK 0x1001
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/* parameter1: frame number */
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/* parameter2: confidence level (smile 0~100) */
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/* parameter3: confidence level (blink 0~100) */
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#define IHC_SET_FACE_MARK 0x1002
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/* parameter1: coordinate count */
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/* parameter2: coordinate buffer address */
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#define IHC_FRAME_DONE 0x1003
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/* parameter1: frame start number */
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/* parameter2: frame count */
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#define IHC_AA_DONE 0x1004
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#define IHC_NOT_READY 0x1005
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#define IH_REPLY_DONE 0x2000
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#define IH_REPLY_NOT_DONE 0x2001
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enum fimc_is_scenario {
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IS_SC_PREVIEW_STILL,
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IS_SC_PREVIEW_VIDEO,
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IS_SC_CAPTURE_STILL,
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IS_SC_CAPTURE_VIDEO,
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IS_SC_MAX
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};
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enum fimc_is_sub_scenario {
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IS_SC_SUB_DEFAULT,
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IS_SC_SUB_PS_VTCALL,
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IS_SC_SUB_CS_VTCALL,
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IS_SC_SUB_PV_VTCALL,
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IS_SC_SUB_CV_VTCALL,
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};
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struct is_common_regs {
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u32 hicmd;
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u32 hic_sensorid;
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u32 hic_param[4];
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u32 reserved1[4];
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u32 ihcmd;
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u32 ihc_sensorid;
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u32 ihc_param[4];
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u32 reserved2[4];
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u32 isp_sensor_id;
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u32 isp_param[2];
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u32 reserved3[1];
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u32 scc_sensor_id;
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u32 scc_param[2];
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u32 reserved4[1];
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u32 dnr_sensor_id;
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u32 dnr_param[2];
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u32 reserved5[1];
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u32 scp_sensor_id;
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u32 scp_param[2];
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u32 reserved6[29];
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} __packed;
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struct is_mcuctl_reg {
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u32 mcuctl;
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u32 bboar;
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u32 intgr0;
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u32 intcr0;
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u32 intmr0;
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u32 intsr0;
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u32 intmsr0;
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u32 intgr1;
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u32 intcr1;
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u32 intmr1;
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u32 intsr1;
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u32 intmsr1;
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u32 intcr2;
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u32 intmr2;
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u32 intsr2;
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u32 intmsr2;
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u32 gpoctrl;
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u32 cpoenctlr;
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u32 gpictlr;
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u32 reserved[0xd];
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struct is_common_regs common;
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} __packed;
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#endif /* FIMC_IS_CMD_H_ */
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