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b452dfe92f
Check the MD_CLK pin to determine the current clock mode in order to set the pll clock parent correctly. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
127 lines
3.2 KiB
C
127 lines
3.2 KiB
C
/*
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* rz Core CPG Clocks
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*
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* Copyright (C) 2013 Ideas On Board SPRL
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* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk/renesas.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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struct rz_cpg {
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struct clk_onecell_data data;
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void __iomem *reg;
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};
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#define CPG_FRQCR 0x10
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#define CPG_FRQCR2 0x14
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#define PPR0 0xFCFE3200
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#define PIBC0 0xFCFE7000
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#define MD_CLK(x) ((x >> 2) & 1) /* P0_2 */
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/* -----------------------------------------------------------------------------
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* Initialization
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*/
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static u16 __init rz_cpg_read_mode_pins(void)
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{
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void __iomem *ppr0, *pibc0;
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u16 modes;
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ppr0 = ioremap_nocache(PPR0, 2);
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pibc0 = ioremap_nocache(PIBC0, 2);
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BUG_ON(!ppr0 || !pibc0);
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iowrite16(4, pibc0); /* enable input buffer */
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modes = ioread16(ppr0);
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iounmap(ppr0);
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iounmap(pibc0);
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return modes;
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}
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static struct clk * __init
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rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name)
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{
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u32 val;
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unsigned mult;
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static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };
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if (strcmp(name, "pll") == 0) {
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unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins());
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const char *parent_name = of_clk_get_parent_name(np, cpg_mode);
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mult = cpg_mode ? (32 / 4) : 30;
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return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);
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}
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/* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
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if (!cpg->reg)
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return ERR_PTR(-ENXIO);
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/* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
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* and the constraint that always g <= i. To get the rz platform started,
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* let them run at fixed current speed and implement the details later.
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*/
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if (strcmp(name, "i") == 0)
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val = (clk_readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
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else if (strcmp(name, "g") == 0)
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val = clk_readl(cpg->reg + CPG_FRQCR2) & 3;
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else
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return ERR_PTR(-EINVAL);
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mult = frqcr_tab[val];
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return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3);
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}
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static void __init rz_cpg_clocks_init(struct device_node *np)
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{
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struct rz_cpg *cpg;
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struct clk **clks;
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unsigned i;
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int num_clks;
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num_clks = of_property_count_strings(np, "clock-output-names");
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if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
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return;
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cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
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clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL);
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BUG_ON(!cpg || !clks);
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cpg->data.clks = clks;
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cpg->data.clk_num = num_clks;
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cpg->reg = of_iomap(np, 0);
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for (i = 0; i < num_clks; ++i) {
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const char *name;
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struct clk *clk;
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of_property_read_string_index(np, "clock-output-names", i, &name);
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clk = rz_cpg_register_clock(np, cpg, name);
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if (IS_ERR(clk))
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pr_err("%s: failed to register %s %s clock (%ld)\n",
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__func__, np->name, name, PTR_ERR(clk));
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else
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cpg->data.clks[i] = clk;
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}
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of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
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cpg_mstp_add_clk_domain(np);
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}
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CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
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